公开(公告)号：US20210035936A1

公开(公告)日：2021-02-04

申请号：US16529796

申请日：2019-08-02

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a substrate, a redistribution layer (RDL) structure, a first die, an encapsulant and a plurality of conductive terminals. The RDL structure is disposed on and electrically connected to the substrate. A width of the RDL structure is less than a width of the substrate. The first die is disposed on the substrate and the RDL structure. The first connectors of the first die are electrically connected to the RDL structure. The second connectors of the first die are electrically connected to the substrate. A first pitch of two adjacent first connectors is less than a second pitch of two adjacent second connectors. The encapsulant is on the substrate to encapsulate the RDL structure and the first die. The conductive terminals are electrically connected to the first die through the substrate and the RDL structure.

公开(公告)号：US20200328167A1

公开(公告)日：2020-10-15

申请号：US16698869

申请日：2019-11-27

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01Q1/22

Abstract: An integrated antenna package structure including a chip package and an antenna device is provided. The antenna device is disposed on the chip package. The chip package includes a chip, an encapsulant, a circuit layer, and a conductive connector. The encapsulant at least directly covers the back side of the chip. The circuit layer is disposed on the encapsulant and electrically connected to the chip. The conductive connector penetrates the encapsulant and is electrically connected to the circuit layer. The antenna device includes a dielectric body, a coupling layer, and an antenna layer. The dielectric body has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The coupling layer is disposed on the second dielectric surface of the dielectric body. The antenna layer is disposed on the first dielectric surface of the dielectric body. The antenna layer is electrically connected to the conductive connector. A manufacturing method of an integrated antenna package structure is also provided.

公开(公告)号：US20200328144A1

公开(公告)日：2020-10-15

申请号：US16382229

申请日：2019-04-12

Applicant: Powertech Technology Inc.

Inventor： Wen-Jeng Fan ,  Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/66 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed aside the semiconductor chip, a conductive via disposed on and electrically connected to the conductive element, an insulating encapsulation, and a first circuit structure disposed on the semiconductor chip and the conductive via is provided. A height of the conductive element is less than a height of the semiconductor chip. The insulating encapsulation encapsulates the semiconductor chip, the conductive element, and the conductive via. The conductive via is located between the first circuit structure and the conductive element, and the semiconductor chip is electrically coupled to the conductive via through the first circuit structure.

公开(公告)号：US10802068B2

公开(公告)日：2020-10-13

申请号：US16213464

申请日：2018-12-07

Applicant: Powertech Technology Inc.

Inventor： Chu Yuan Mo

IPC: G01R31/28 ,  G01R3/00

Abstract: A method of detecting abnormal test signal channel of automatic test equipment firstly obtains a raw test data and then divides into the data groups according to a mapping data. The test data of DUTs in one data group are generated by the same group of probes. A yield of each data group is further estimated. A yield of a wafer is further estimated when the yield of the data group matches a first failure threshold. An abnormal test signal channel is determined when the yield of the wafer does not match a second failure threshold or the yield of the wafer matches the normal threshold. Therefore, to add the detecting method in an original test procedure of the ATE, the operator easily identifies which blocks in the failure color on the test data map are caused by the abnormal test signal channel.

公开(公告)号：US20200321259A1

公开(公告)日：2020-10-08

申请号：US16417671

申请日：2019-05-21

Applicant: Powertech Technology Inc.

Inventor： Chih-Yen Su ,  Chun-Te Lin

IPC: H01L23/31 ,  H01L23/00

Abstract: A semiconductor package structure includes a substrate, a chip, and an encapsulant. The chip is disposed on the substrate. The encapsulant is disposed on the substrate and covers the chip. The encapsulant has a top surface away from the substrate and at least one protruding strip protruding from the top surface.

公开(公告)号：US10607856B2

公开(公告)日：2020-03-31

申请号：US15626165

申请日：2017-06-18

Applicant: Powertech Technology Inc.

Inventor： Kun-Yung Huang ,  Chih-Fu Lung ,  Shih-Chi Li ,  Mei-Chen Lee ,  Chung-Hao Tsai ,  Chi-Liang Wang

IPC: H05K3/02 ,  H01L21/48 ,  H01L21/683

Abstract: A manufacturing method of a redistribution layer is provided. The method includes the following steps. A patterned sacrificial layer is formed on a carrier. An actuate angle is formed between a side wall of the patterned sacrificial layer and the carrier. A first conductive layer is formed. The first conductive layer includes a plurality of first portions formed on the carrier and a plurality of second portions formed on the patterned sacrificial layer. The patterned sacrificial layer and the second portions of the first conductive layer are removed from the carrier. Another manufacturing method of a redistribution layer is also provided.

公开(公告)号：US20200091103A1

公开(公告)日：2020-03-19

申请号：US16136197

申请日：2018-09-19

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps.

公开(公告)号：US20190319000A1

公开(公告)日：2019-10-17

申请号：US15952261

申请日：2018-04-13

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure includes a die, an encapsulant, a dam structure, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The encapsulant encapsulates sidewalls of the die. The encapsulant has a first surface and a second surface opposite to the first surface. The first surface is coplanar with the rear surface of the die. The second surface is located at a level height different from the active surface of the die. The dam structure is disposed on the active surface of the die. A top surface of the dam structure is substantially coplanar with the second surface of the encapsulant. The redistribution structure is over the encapsulant, the dam structure, and the die. The redistribution structure is electrically connected to the die.

公开(公告)号：US20190252325A1

公开(公告)日：2019-08-15

申请号：US16035709

申请日：2018-07-16

Applicant: Powertech Technology Inc.

Inventor： Yu-Wei Chen ,  Hsuan-Chih Chang ,  Yuan-Fu Lan ,  Hsien-Wen Hsu

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19041 ,  H01L2924/19106 ,  H01L2924/3025

Abstract: A chip package structure including a first circuit structure, a chip, an electronic device, a first encapsulant, a second encapsulant, a plurality of through pillars, and an electromagnetic interference (EMI) shielding layer is provided. The chip has an active surface facing the first circuit structure. The electronic device has a connection surface facing the first circuit structure. The chip and the electronic device are disposed on opposite sides of the first circuit structure respectively. The first encapsulant encapsulates the chip. The second encapsulant encapsulates the electronic device. The through pillars penetrate the first encapsulant and are electrically connected to the first circuit structure. The EMI shielding layer covers the first encapsulant and the second encapsulant. The chip or the electronic device is grounded by the EMI shielding layer.

公开(公告)号：US20190164888A1

公开(公告)日：2019-05-30

申请号：US16114237

申请日：2018-08-28

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H01L25/00

Abstract: A package structure including a redistribution structure, a die, a plurality of conductive structures, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The conductive structures are disposed on and electrically connected to the redistribution structure. The conductive structures surround the die. The first insulating encapsulant encapsulates the die and the conductive structures. The first insulating structure includes a plurality of openings exposing top surfaces of the conductive structures. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the conductive structures. The second insulating encapsulant encapsulates the chip stack.