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    SYSTEM AND METHOD OF LOW POWER SWITCH STATE DETECTION
    81.
    发明申请
    SYSTEM AND METHOD OF LOW POWER SWITCH STATE DETECTION 有权

    公开(公告)号：US20220074991A1

    公开(公告)日：2022-03-10

    申请号：US17100286

    申请日：2020-11-20

    Applicant: Silicon Laboratories Inc.

    Inventor： Matthew R. Williamson ,  Sebastian Ahmed

    IPC: G01R31/327 ,  H03K19/21 ,  H03K5/24

    Abstract: A switch sensor for sensing a state of a switch including a programmable memory, pulse generation circuitry, and comparator circuitry. The memory stores a state value indicative of a detected state of the switch. The pulse generation circuitry provides a pulse-train voltage signal to a first end of the switch, in which the pulse-train voltage signal is toggled between an active state for switch state detection and an inactive state for conserving power. A second terminal of the switch is coupled through resistive circuitry to a supply voltage node and may be coupled to an input terminal of the sensor. The comparator circuitry compares a state of the input terminal with the state value when the pulse-train voltage signal is in the active state for providing a state change signal indicative thereof.

    Frequency modulation tracking for band rejection to reduce dynamic range
    83.
    发明授权
    Frequency modulation tracking for band rejection to reduce dynamic range 有权

    公开(公告)号：US11258643B1

    公开(公告)日：2022-02-22

    申请号：US17323782

    申请日：2021-05-18

    Applicant: Silicon Laboratories Inc.

    Inventor： Alexander August Arthur Hakkola

    IPC: H04B1/10 ,  H04L27/14

    Abstract: In at least one embodiment of the invention, a method for reducing a dynamic range of a received radio frequency signal includes receiving digital IQ signals corresponding to an in-phase component of the received radio frequency signal and a quadrature component of the received radio frequency signal. The method includes demodulating the digital IQ signals to generate an instantaneous frequency signal. The method includes selecting a center frequency of a selectable filter according to whether an interfering signal is detected in a target frequency band of the received radio frequency signal. The center frequency is selected from a predetermined frequency and an estimated center frequency determined using the instantaneous frequency signal. The method includes filtering the digital IQ signals using the selectable filter configured using the center frequency to generate output digital IQ signals.

    Deglitcher circuit with integrated non-overlap function
    84.
    发明授权
    Deglitcher circuit with integrated non-overlap function 有权

    公开(公告)号：US11258432B1

    公开(公告)日：2022-02-22

    申请号：US17125561

    申请日：2020-12-17

    Applicant: Silicon Laboratories Inc.

    Inventor： Péter Onódy ,  András V. Horváth

    IPC: H03K5/125 ,  H03K5/1252 ,  H03H11/06 ,  H03H11/26 ,  H03K3/012 ,  H03K17/687 ,  H03K19/20

    Abstract: A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

    Packet Synchronization Information Peeking
    87.
    发明申请
    Packet Synchronization Information Peeking 有权

    公开(公告)号：US20220022132A1

    公开(公告)日：2022-01-20

    申请号：US16928356

    申请日：2020-07-14

    Applicant: Silicon Laboratories Inc.

    Inventor： Jere M. Knaappila

    IPC: H04W52/02 ,  H04W56/00

    Abstract: A device, method and software program that allows a network device to remain synchronized to a master device while minimizing its own power consumption is disclosed. The network device exits a low power mode at regular intervals in order to receive a synchronous communication from a master device. Once the network device has received enough information to confirm that this synchronous communication is from the correct master device, the network device may then return to the low power mode, even before the entirety of the synchronous communication has been received. This may reduce the time that the network device is in the active state by more than 90% in certain instances.

    End node spectrogram compression for machine learning speech recognition
    88.
    发明授权
    End node spectrogram compression for machine learning speech recognition 有权

    公开(公告)号：US11227614B2

    公开(公告)日：2022-01-18

    申请号：US16898806

    申请日：2020-06-11

    Applicant: Silicon Laboratories Inc.

    Inventor： Antonio Torrini ,  Sebastian Ahmed

    IPC: G10L19/02 ,  G10L25/18

    Abstract: A system and method of recording and transmitting compressed audio signals over a network is disclosed. The end node device first converts the audio signal to a spectrogram, which is commonly used by machine learning algorithms to perform speech recognition. The end node device then compresses the spectrogram prior to transmission. In certain embodiments, the compression is performed using Discrete Cosine Transforms (DCT). Furthermore, in some embodiments, the DCT is performed on the difference between two columns of the spectrogram. Further, in some embodiments, a function that replaces values below a predetermined threshold with zeroes in the Encoded Spectrogram is utilized. These functions may be performed in hardware or software.

    Variable rate sampling for AGC in a bluetooth receiver using connection state and access address field
    89.
    发明授权
    Variable rate sampling for AGC in a bluetooth receiver using connection state and access address field 有权

    公开(公告)号：US11206122B1

    公开(公告)日：2021-12-21

    申请号：US17106111

    申请日：2020-11-29

    Applicant: Silicon Laboratories, Inc.

    Inventor： Sriram Mudulodu

    IPC: H04L7/00 ,  H04B1/12 ,  H03M1/12

    Abstract: A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.

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