公开(公告)号：US20180018133A1

公开(公告)日：2018-01-18

申请号：US15272626

申请日：2016-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0683 ,  G06F13/1673

Abstract: In one form, an apparatus includes a memory controller. The memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter picks the memory access requests from the command queue based on a plurality of criteria, and provides picked memory access requests to a memory channel. The arbiter includes a streak counter for counting a number of consecutive memory access requests of a first type that the arbiter picks from the command queue. When the streak counter reaches a threshold, the arbiter suspends picking requests of the first type and picks at least one memory access request of a second type. The arbiter provides the at least one memory access request of the second type to the memory channel.

公开(公告)号：US09576637B1

公开(公告)日：2017-02-21

申请号：US15164721

申请日：2016-05-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan

IPC: G11C7/00 ,  G11C11/00 ,  G11C11/406 ,  G06F3/06

CPC classification number: G11C11/40611 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0679 ,  G11C11/40603 ,  G11C11/40615

Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. In response to an activation of the refresh logic, the data processor generates refresh cycles to a bank of the memory channel. The data processor selects one of a first state corresponding to a first auto-refresh command that causes the data processor to auto-refresh the bank, and a second state corresponding to a second auto-refresh command that causes the data processor to auto-refresh a selected subset of the bank. The data processor initiates a switch between the first state and the second state in response to the refresh logic detecting a first condition related to the bank, and between the second state and the first state in response to the refresh logic circuit detecting a second condition.

Abstract translation: 数据处理系统包括存储器通道和耦合到存储器通道的数据处理器。 数据处理器适于访问至少一个等级并具有刷新逻辑。 响应于刷新逻辑的激活，数据处理器向存储器通道的存储体生成刷新周期。 数据处理器选择与导致数据处理器自动刷新存储体的第一自动刷新命令相对应的第一状态中的一个状态，以及与引起数据处理器自动刷新的第二自动刷新命令相对应的第二状态 银行的选定子集。 数据处理器响应于刷新逻辑检测与存储体相关的第一条件以及在第二状态和第一状态之间响应于刷新逻辑电路检测到第二条件而启动在第一状态和第二状态之间的切换。