公开(公告)号：US20230198772A1

公开(公告)日：2023-06-22

申请号：US17555020

申请日：2021-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Andrew G. Kegel

IPC: H04L9/32 ,  G06N3/08

CPC classification number: H04L9/3239 ,  G06N3/08

Abstract: An approach is provided for implementing a useful proof-of-work consensus algorithm. A proposed block is received. A combined hash value is generated based on the proposed block and a nonce value. The combined hash value is divided into a plurality of hash value pieces that each correspond to a work packet of a plurality of work packets. One or more requests are transmitted for the plurality of work packets that correspond to the plurality of hash value pieces. In response to receiving the plurality of work packets, a plurality of results is generated by performing, for each work packet of the plurality of work packets, one or more operations to complete work specified by the respective work packet. In response to determining that at least one result of the plurality of results satisfies one or more criteria, the proposed block is added to a blockchain maintained by the blockchain network.

公开(公告)号：US20220188185A1

公开(公告)日：2022-06-16

申请号：US17118434

申请日：2020-12-10

Applicant: Advanced Micro Devices, Inc.

Inventor： SeyedMohammad SeyedzadehDelcheh ,  Sergey Blagodurov

IPC: G06F11/10

Abstract: An apparatus and method for efficiently transmitting data are described. A transmitter sends data to a receiver. An encoder of the transmitter divides a received first block of data into multiple sub-blocks. The encoder selects a portion of each sub-block to compare to one another. A portion in a particular sub-block has a same offset and a same size as other portions of other sub-blocks. If the encoder determines the multiple portions match one another, the encoder sends, to the receiver, a second block of data corresponding to the first block of data. The second block of data has a same size as a size of the received first block of data, and the second block of data includes security data from one of multiple error correction schemes. Therefore, the second block of data provides security without increasing an amount of data to transmit.

公开(公告)号：US11341059B2

公开(公告)日：2022-05-24

申请号：US16894473

申请日：2020-06-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Andrew G. Kegel

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/1027 ,  G06F3/06

Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.

公开(公告)号：US11237928B2

公开(公告)日：2022-02-01

申请号：US16700993

申请日：2019-12-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Michael Ignatowski ,  Vilas Sridharan

IPC: G06F11/00 ,  G06F11/20

Abstract: A method includes reserving memory capacity in a first memory device as patch memory region for backing faulted memory, receiving a memory error indication indicating an uncorrectable error in a faulted segment in a second memory device and, in response to the memory error indication, associating in a remapping table the faulted segment with a patch segment in the patch memory region. The faulted segment is smaller than a memory page size of the second memory device. The method also includes, in response to receiving a memory access request directed to the faulted memory segment, servicing the memory access request from the patch segment by querying the remapping table to determine a patch segment address corresponding to a requested memory address, where the patch segment address identifies the location of the patch segment, and based on the patch segment address, performing the requested memory access at the patch segment.

公开(公告)号：US20210409488A1

公开(公告)日：2021-12-30

申请号：US17347116

申请日：2021-06-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov

IPC: H04L29/08 ,  H04L12/24 ,  H04L12/725

Abstract: A server includes a plurality of nodes that are connected by a network that includes an on-chip network or an inter-chip network that connects the nodes. The server also includes a controller to configure the network based on relative priorities of workloads that are executing on the nodes. Configuring the network can include allocating buffers to virtual channels supported by the network based on the relative priorities of the workloads associated with the virtual channels, configuring routing tables that route the packets over the network based on the relative priorities of the workloads that generate the packets, or modifying arbitration weights to favor granting access to the virtual channels to packets generated by higher priority workloads.

公开(公告)号：US20210097014A1

公开(公告)日：2021-04-01

申请号：US16588612

申请日：2019-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Antonio Maria Franques Garcia

IPC: G06F13/40 ,  H04L12/751 ,  H04L12/841 ,  H04W72/00 ,  H04L12/46 ,  H04W28/02 ,  H04W40/10

Abstract: Systems, apparatuses, and methods for dynamically selecting between wired and wireless interconnects for sending packets are disclosed. A system includes at least a hybrid communication engine and a plurality of interconnects for connecting to various end-points. The communication engine dynamically discovers and utilizes the best interconnect technology available in between given end-points. The communication engine dynamically chooses the physical interconnect that is best suited at any given time to send data from one source to one or multiple destinations. This communication can be either on-chip or across nodes. The communication engine makes a decision based on a set of predetermined parameters that can be re-adjusted by the application layer, such as latency of the transmission, message data size, physical distance from source to destination, the energy cost, and the current congestion on the alternative interconnects.

公开(公告)号：US10761986B2

公开(公告)日：2020-09-01

申请号：US16168315

申请日：2018-10-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Timothy E. Landreth ,  Stanley Ames Lackey, Jr. ,  Patrick Conway

IPC: G06F12/0815 ,  G06F3/06

Abstract: A data processing system includes a host processor, a local memory coupled to the host processor, a plurality of remote memory media, and a scalable data fabric coupled to the host processor and to the plurality of remote memory media. The scalable data fabric includes a filter for storing information indicating a location of data that is stored by the data processing system. The host processor includes a hardware sequencer coupled to the filter for selectively moving data stored by the filter to the local memory.

公开(公告)号：US20200125490A1

公开(公告)日：2020-04-23

申请号：US16168315

申请日：2018-10-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Timothy E. Landreth ,  Stanley Ames Lackey, JR. ,  Patrick Conway

IPC: G06F12/0815 ,  G06F3/06

Abstract: A data processing system includes a host processor, a local memory coupled to the host processor, a plurality of remote memory media, and a scalable data fabric coupled to the host processor and to the plurality of remote memory media. The scalable data fabric includes a filter for storing information indicating a location of data that is stored by the data processing system. The host processor includes a hardware sequencer coupled to the filter for selectively moving data stored by the filter to the local memory.

公开(公告)号：US20190310864A1

公开(公告)日：2019-10-10

申请号：US15948795

申请日：2018-04-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Anthony T. Gutierrez ,  Sergey Blagodurov ,  Scott A. Moe ,  Xianwei Zhang ,  Jieming Yin ,  Matthew D. Sinclair

IPC: G06F9/445 ,  G06N3/10 ,  G06N3/08 ,  G06N3/04

Abstract: An electronic device includes a controller functional block and a computational functional block. During operation, while the computational functional block executes a test portion of a workload at at least one precision level, the controller functional block monitors a behavior of the computational functional block. Based on the behavior of the computational functional block while executing the test portion of the workload at the at least one precision level, the controller functional block selects a given precision level from among a set of two or more precision levels at which the computational functional block is to execute a remaining portion of the workload. The controller functional block then configures the computational block to execute the remaining portion of the workload at the given precision level.

公开(公告)号：US10318340B2

公开(公告)日：2019-06-11

申请号：US14587325

申请日：2014-12-31

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Gabriel H. Loh ,  Mauricio Breternitz

IPC: G06F12/02 ,  G06F9/48 ,  G11C11/00 ,  G06F12/0811

Abstract: In one form, a computer system includes a central processing unit, a memory controller coupled to the central processing unit and capable of accessing non-volatile random access memory (NVRAM), and an NVRAM-aware operating system. The NVRAM-aware operating system causes the central processing unit to selectively execute selected ones of a plurality of application programs, and is responsive to a predetermined operation to cause the central processing unit to execute a memory persistence procedure using the memory controller to access the NVRAM.