公开(公告)号：US20130330906A1

公开(公告)日：2013-12-12

申请号：US13490635

申请日：2012-06-07

Applicant: Weibo Yu ,  Ming-His Yeh ,  Chih-Tang Peng ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Syun-Ming Jang

Inventor： Weibo Yu ,  Ming-His Yeh ,  Chih-Tang Peng ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.

Abstract translation: 公开了制造半导体IC的方法。 该方法包括接收设备。 该器件包括半导体衬底，半导体衬底中的翅片之间的多个散热片和沟槽。 该方法还包括用介电材料填充沟槽以形成浅沟槽隔离（STI），对介电材料施加低热预算退火，以及对电介质材料进行湿法处理。

公开(公告)号：US20130277759A1

公开(公告)日：2013-10-24

申请号：US13452516

申请日：2012-04-20

Applicant: Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Chia Tai Lin ,  Chao-Cheng Chen

Inventor： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Chia Tai Lin ,  Chao-Cheng Chen

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/6681

Abstract: A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region.

Abstract translation: 一种器件包括半导体衬底和彼此平行的多个半导体鳍片，其中多个半导体鳍片是半导体衬底的一部分。 浅沟槽隔离（STI）区域位于多个半导体鳍片的一侧。 STI区域具有顶表面和非平坦底表面，其中多个半导体鳍片在STI区域的顶表面之上。

公开(公告)号：US20130078809A1

公开(公告)日：2013-03-28

申请号：US13244337

申请日：2011-09-24

Applicant: Weibo Yu ,  Hsueh-Chin Lu ,  Han-Guan Chew ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

Inventor： Weibo Yu ,  Hsueh-Chin Lu ,  Han-Guan Chew ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L21/306

CPC classification number: H01L21/6708 ,  H01L21/31111

Abstract: A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture.

Abstract translation: 公开了在单晶片蚀刻装置中实现的单晶片蚀刻装置和各种方法。 在一个实施例中，在单晶片蚀刻装置中蚀刻氮化硅层包括：将磷酸加热到第一温度; 将硫酸加热至第二温度; 混合加热的磷酸和加热的硫酸; 将磷酸/硫酸混合物加热至第三温度; 并用加热的磷酸/硫酸混合物蚀刻氮化硅层。

公开(公告)号：US08258588B2

公开(公告)日：2012-09-04

申请号：US12757241

申请日：2010-04-09

Applicant: Yu Chao Lin ,  Jr Jung Lin ,  Yih-Ann Lin ,  Jih-Jse Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Chang

Inventor： Yu Chao Lin ,  Jr Jung Lin ,  Yih-Ann Lin ,  Jih-Jse Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Chang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/4983 ,  H01L29/6656

Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

Abstract translation: 场效应晶体管的栅极结构的示例性结构包括栅电极; 栅电极下方的栅极绝缘体，在栅电极的相对侧具有基极区域; 以及在所述栅极结构的侧壁上的密封层，其中覆盖所述基底区域的所述密封层的下部的厚度小于所述栅极电极的侧壁上的所述密封层的上部的厚度，由此所述场效应晶体管 在基板表面几乎没有凹陷。

公开(公告)号：US20110049567A1

公开(公告)日：2011-03-03

申请号：US12841763

申请日：2010-07-22

Applicant: Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

Inventor： Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66636

Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.

Abstract translation: 本公开提供了一种制造半导体器件的方法，其包括提供硅衬底，在硅衬底上形成栅极堆叠，对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分，从而形成凹陷区域 在硅衬底中，对硅衬底中的凹部进行无偏压蚀刻工艺，从而在硅衬底中形成瓶颈形凹部区域，并且在瓶颈形凹部区域中形成半导体材料 在硅衬底中。 一个实施例可以包括偏置的干蚀刻工艺，包括加入HeO2气体和HBr气体。 实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺，并执行不包括N 2气体的第二偏压干式蚀刻工艺。 一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅，来对硅衬底中的凹陷区域进行氧化处理。 因此，这些方法形成聚合物保护以帮助形成瓶颈形凹部。

公开(公告)号：US20100190349A1

公开(公告)日：2010-07-29

申请号：US12798201

申请日：2010-03-30

Applicant: Huang-Ming Chen ,  Chun-Li Chou ,  Chao-Cheng Chen ,  Hun-Jan Tao

Inventor： Huang-Ming Chen ,  Chun-Li Chou ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC: H01L21/465 ,  C23F1/00

CPC classification number: H01L21/68735 ,  H01J37/3244 ,  H01J37/32642 ,  H01L21/02046 ,  H01L21/31116 ,  H01L21/67069 ,  Y10S156/914 ,  Y10S156/915 ,  Y10T279/23

Abstract: A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method further provides delivering oxygen gas to the substrate by mixing oxygen in the cooling gas mixture, maintaining the focus ring at a temperature no greater than the substrate temperature during etching and cleaning the substrate using a two step plasma cleaning sequence that includes suspending the substrate above the chuck.

Abstract translation: 防止在半导体衬底的背面形成污染性聚合物膜的方法包括提供在蚀刻操作期间释放氧气的氧浸渍聚焦环和/或氧浸渍卡盘。 该方法还通过在冷却气体混合物中混合氧将氧气输送到衬底，在蚀刻和清洁衬底期间将聚焦环保持在不高于衬底温度的温度，使用包括悬浮衬底的两步骤等离子体清洗序列 在卡盘上方

公开(公告)号：US07538025B2

公开(公告)日：2009-05-26

申请号：US10714304

申请日：2003-11-14

Applicant: Chao-Cheng Chen ,  Chen-Nan Yeh ,  Chien-Chung Fu

Inventor： Chao-Cheng Chen ,  Chen-Nan Yeh ,  Chien-Chung Fu

IPC: H01L21/4763

CPC classification number: H01L21/76808 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/31695

Abstract: A method of forming a dual damascene opening comprising the following steps. A structure having an overlying exposed conductive layer formed thereover is provided. A dielectric layer is formed over the exposed conductive layer. An anti-reflective coating layer is formed over the dielectric layer. The anti-reflective layer and the dielectric layer are etched using a via opening process to form an initial via exposing a portion of the conductive layer. A protective film portion is formed over at least the exposed portion of the conductive layer. The anti-reflective coating layer and the dielectric layer are patterned to reduce the initial via to a reduced via and to form a trench opening substantially centered over the reduced via. The trench opening and the reduced via comprising the dual damascene opening.

Abstract translation: 一种形成双镶嵌开口的方法，包括以下步骤。 提供一种其上形成有上覆的暴露的导电层的结构。 在暴露的导电层上形成电介质层。 在电介质层上形成抗反射涂层。 使用通孔打开工艺蚀刻抗反射层和电介质层，以形成暴露导电层的一部分的初始通孔。 至少在导电层的暴露部分上形成保护膜部分。 将抗反射涂层和电介质层图案化以将初始通孔减小到减小的通孔，并形成基本上位于经过还原通孔的中心的沟槽开口。 沟槽开口和通孔包括双镶嵌开口。

公开(公告)号：US20090045482A1

公开(公告)日：2009-02-19

申请号：US11838666

申请日：2007-08-14

Applicant: Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

Inventor： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

IPC: H01L29/00

CPC classification number: H01L21/823878 ,  H01L21/76232

Abstract: A shallow trench isolation (STI) structure has a top portion tapering in width from wide to narrow in a direction from a substrate surface, from a first width at a top of the first portion to a second width at a bottom of the first portion. The STI structure also includes a bottom portion below the top portion, which expands from the bottom of the top portion to a substantially widened lateral distance having a third width. The third width is, in general, substantially larger than the second width. The inventive STI structure can provide desired isolation characteristics with a significantly reduced aspect ratio, thus suitable for device isolations in advanced processing technology.

Abstract translation: 浅沟槽隔离（STI）结构具有在从基板表面的方向上从宽到窄的宽度从第一部分的顶部处的第一宽度到第一部分的底部处的第二宽度的顶部部分。 STI结构还包括在顶部下方的底部，其从顶部的底部膨胀到具有第三宽度的基本上加宽的横向距离。 通常，第三宽度基本上大于第二宽度。 本发明的STI结构可以提供期望的隔离特性，具有显着减小的纵横比，因此适用于先进加工技术中的器件隔离。

公开(公告)号：US20060081917A1

公开(公告)日：2006-04-20

申请号：US10964841

申请日：2004-10-13

Applicant: Chien-Hao Chen ,  Chia-Jen Chen ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Chia-Jen Chen ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Shih-Chang Chen

IPC: H01L29/76

CPC classification number: H01L21/28123 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/31608 ,  H01L21/3185

Abstract: A method for forming a hard mask for gate electrode patterning in a semiconductor device is disclosed. The method includes providing a polysilicon layer to be etched and forming over the polysilicon layer, a nitride hardmask with a relatively high etch rate to hydrofluoric acid, as compared to the etch rate of silicon oxide. The polysilicon can then be patterned using the hardmask and the hardmask can be removed using hydrofluoric acid.

Abstract translation: 公开了一种在半导体器件中形成用于栅电极图案化的硬掩模的方法。 该方法包括提供待蚀刻并在多晶硅层上形成的多晶硅层，与氧化硅的蚀刻速率相比，具有对氢氟酸的蚀刻速率相对较高的氮化物硬掩模。 然后可以使用硬掩模对多晶硅进行图案化，并且可以使用氢氟酸去除硬掩模。

公开(公告)号：US20060003576A1

公开(公告)日：2006-01-05

申请号：US10882058

申请日：2004-06-30

Applicant: Chen-Nan Yeh ,  Tsiao-Chen Wu ,  Chao-Cheng Chen

Inventor： Chen-Nan Yeh ,  Tsiao-Chen Wu ,  Chao-Cheng Chen

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76801 ,  H01L21/76808 ,  H01L2221/1026 ,  H01L2221/1031

Abstract: A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask layer and organic dielectric layer to leave a dummy portion overlying the via opening; forming an oxide liner over the dummy portion; forming a second dielectric insulating layer over the oxide liner to surround the dummy portion; planarizing the second dielectric insulating layer to expose the upper portion of the dummy portion; and, removing the organic dielectric layer to form a dual damascene opening including the oxide liner lining trench line portion sidewalls.

Abstract translation: 一种用于形成双镶嵌的方法，包括提供包括通孔的第一介电绝缘层; 在所述第一IMD层上形成有机介电层以包括填充所述通孔; 在有机介电层上形成硬掩模层; 光刻图案化和干蚀刻硬掩模层和有机电介质层以留下覆盖通孔开口的虚拟部分; 在所述虚拟部分上形成氧化物衬垫; 在所述氧化物衬垫上形成围绕所述虚拟部分的第二介电绝缘层; 平面化第二介电绝缘层以暴露虚设部分的上部; 并且去除有机电介质层以形成包括氧化物衬里衬里沟槽部分侧壁的双镶嵌开口。