公开(公告)号：US10153253B2

公开(公告)日：2018-12-11

申请号：US15357233

申请日：2016-11-21

Applicant: Intel Corporation

Inventor： Howe Yin Loo ,  Eng Huat Goh ,  Min Suet Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/16 ,  H01L25/00 ,  H05K1/11 ,  H05K3/30 ,  H05K3/36 ,  H05K1/14

Abstract: A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a through-mold via package bottom interposer disposed on the package substrate on a land side. A land side board mates with the through-mold via package bottom interposer, and enough vertical space is created by the through-mold via package bottom interposer to allow space for at least one device disposed on the package substrate on the land side.

公开(公告)号：US10083922B2

公开(公告)日：2018-09-25

申请号：US15359926

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Chin Lee Kuan ,  Eng Huat Goh ,  Khang Choong Yong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Howe Yin Loo

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors. An integrated circuit package attached to a motherboard using spiral interconnects is shown. Methods of attaching an integrated circuit package to a motherboard using spiral interconnects are shown including air core inductors. Methods of attaching spiral interconnects include using electrically conductive adhesive or solder.

公开(公告)号：US20180097056A1

公开(公告)日：2018-04-05

申请号：US15282504

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Han Kung Chua ,  Min Suet Lim ,  Hoay Tien Teoh

IPC: H01L49/02

CPC classification number: H01L28/75

Abstract: A three capacitor stack and associated methods are shown. An exemplary capacitor device may include a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes, a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes, and a third capacitor stack on the second capacitor stack that includes a reference electrode and a third capacitor electrode. A respective layer of dielectric material is formed between the reference electrodes and the first capacitor electrodes, the second capacitor electrodes, and the third capacitor electrode.

公开(公告)号：US20170359893A1

公开(公告)日：2017-12-14

申请号：US15182091

申请日：2016-06-14

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Fern Nee Tan ,  Khang Choong Yong ,  Jiun Hann Sir

IPC: H05K1/02 ,  H01G4/008 ,  H01L23/00 ,  H01G4/12 ,  H01L21/48 ,  H05K1/18 ,  H05K1/11 ,  H01G4/30 ,  H05K1/09 ,  H01L23/498

CPC classification number: H05K1/0231 ,  H01G4/1209 ,  H01G4/228 ,  H01G4/33 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/19041 ,  H01L2924/19102 ,  H05K1/141 ,  H05K2201/10015 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops. The capacitive interconnects can be utilized in a semiconductor package, providing a compact assembly that can reduce the utilization of real estate in a board substrate onto which the semiconductor package is mounted.

公开(公告)号：US20160118354A1

公开(公告)日：2016-04-28

申请号：US14986542

申请日：2015-12-31

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Hoay Tien Teoh

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L24/02 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/0105 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

Abstract translation: 一种微电子封装，其具有邻近微电子器件的有源表面和侧面的第一无凸起的构建层结构和邻近微电子器件的后表面的第二无扰动积聚层结构，其中通过第一无扰动构建形成导电路径 从微电子器件有源表面到第二无扰性积聚层结构中的导电路径的上层，并且其中邻近微电子器件背表面并延伸到微电子器件中的穿硅通孔电连接到第二无扰动积聚层 结构导电路线。

公开(公告)号：US20240234234A9

公开(公告)日：2024-07-11

申请号：US17972923

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Ilan Ronen ,  Kavitha Nagarajan ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong

IPC: H01L23/367 ,  H01L23/42 ,  H01L23/532

CPC classification number: H01L23/367 ,  H01L23/42 ,  H01L23/53233

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.

公开(公告)号：US20240136279A1

公开(公告)日：2024-04-25

申请号：US17972975

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong ,  Kavitha Nagarajan

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L28/10

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.

公开(公告)号：US20240136243A1

公开(公告)日：2024-04-25

申请号：US17972923

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Ilan Ronen ,  Kavitha Nagarajan ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong

IPC: H01L23/367 ,  H01L23/42 ,  H01L23/532

CPC classification number: H01L23/367 ,  H01L23/42 ,  H01L23/53233

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.

公开(公告)号：US11823994B2

公开(公告)日：2023-11-21

申请号：US17671478

申请日：2022-02-14

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/50 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L23/31 ,  H01L23/49866 ,  H01L23/50 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package. For instance, in accordance with one embodiment, there is a substrate package having embodied therein a functional silicon die at a top layer of the substrate package; a solder resist layer beneath the functional silicon die of the substrate package; a plurality of die bumps at a bottom surface of the functional silicon die, the plurality of die bumps electrically interfacing the functional silicon die to a substrate through a plurality of solder balls at a top surface of the solder resist layer; each of the plurality of die bumps electrically interfaced to a nickel pad at least partially within the solder resist layer and beneath the solder balls; each of the plurality of die bumps electrically interfaced through the nickel pads to a conductive pad exposed at a bottom surface of the solder resist layer; and in which each of the conductive pads exposed at the bottom surface of the solder resist layer are electrically interfaced to an electrical trace at the substrate of the substrate package. Other related embodiments are disclosed.

公开(公告)号：US20230369232A1

公开(公告)日：2023-11-16

申请号：US17741988

申请日：2022-05-11

Applicant: Intel Corporation

Inventor： Hazwani Jaffar ,  Poh Boon Khoo ,  Hooi San Lam ,  Jiun Hann Sir ,  Eng Huat Goh

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L23/5385 ,  H01L25/18 ,  H01L25/50 ,  H01L21/4853 ,  H01L25/105

Abstract: An electronic system includes a first substrate including first solder bumps on a bottom surface, the first solder bumps having a first solder bump surface opposite from the bottom surface; a processor integrated circuit (IC) die including at least one processor mounted on a top surface of the first substrate; and a companion component to the processor IC. The companion component includes a second substrate, second solder bumps, and third solder bumps. The second solder bumps include a second solder bump surface, and the third solder bumps include a third solder bump surface at a different height than the second solder bump surface. The second solder bump surface contacts the top surface of the first substrate and the third solder bump surface is at a same height as the first solder bump surface.