公开(公告)号：US20190304053A1

公开(公告)日：2019-10-03

申请号：US16446265

申请日：2019-06-19

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06N20/00 ,  G06F7/483

Abstract: Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple precisions.

公开(公告)号：US20190266351A1

公开(公告)日：2019-08-29

申请号：US16412845

申请日：2019-05-15

Applicant: Intel Corporation

Inventor： John C. Weast ,  Joshua Boelter

IPC: G06F21/62 ,  G09G3/00 ,  G06F21/35 ,  G06F21/84 ,  G06F3/14

Abstract: Technologies for displaying public and private images includes a display device and one or more user viewing devices. The display device is configured to display or generate a personalized image or video that is viewable by an authorized user viewing device and not viewable by unauthorized viewing devices. To facilitate the display of the personalized images, the display device and the user viewing device(s) may negotiate a display protocol to be used by the display device to display the personalized image in a private manner. In some embodiment, the display device may also display a public image or video that is viewable by unauthorized viewing devices and/or individuals without viewing devices.

公开(公告)号：US20190243764A1

公开(公告)日：2019-08-08

申请号：US16277267

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Prasoonkumar Surti ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Abhishek R. Appu ,  Nicolas C. Galoppo Von Borries ,  Joydeep Ray ,  Narayan Srinivasa ,  Feng Chen ,  Ben J. Ashbaugh ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/0837 ,  G06N20/00 ,  G06T1/20 ,  G06N3/08

CPC classification number: G06F12/0837 ,  G06F12/0815 ,  G06F2212/62 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084 ,  G06N3/088 ,  G06N20/00 ,  G06T1/20

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190206020A1

公开(公告)日：2019-07-04

申请号：US16197821

申请日：2018-11-21

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06F7/483 ,  G06N20/00

CPC classification number: G06T1/20 ,  G06F3/14 ,  G06F7/483 ,  G06F9/30014 ,  G06F9/30185 ,  G06F9/3863 ,  G06F9/5044 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/084 ,  G06N20/00 ,  G06T1/60 ,  G06T15/005

Abstract: One embodiment provides an accelerator module comprising a memory stack including multiple memory dies; a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the multiprocessors to execute at least one single instruction. The at least one single instruction is to cause at least a portion of the GPU to perform a floating point operation on input having differing precisions. The floating point operation is a two-dimensional matrix multiply and accumulate operation.

公开(公告)号：US10255656B2

公开(公告)日：2019-04-09

申请号：US15798574

申请日：2017-10-31

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Linda L. Hurd ,  Dukhwan Kim ,  Mike B. Macpherson ,  John C. Weast ,  Feng Chen ,  Farshad Akhbari ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman

IPC: G06T1/20 ,  G06T15/04 ,  G06T15/00 ,  G09G5/36 ,  G06F9/38

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.

公开(公告)号：US20190056232A1

公开(公告)日：2019-02-21

申请号：US16166928

申请日：2018-10-22

Applicant: Intel Corporation

Inventor： Ren Wang ,  Zhonghong Ou ,  Arvind Kumar ,  Kristoffer Fleming ,  Tsung-Yuan C. Tai ,  Timothy J. Gresham ,  John C. Weast ,  Corey Kukis

IPC: G01C21/34 ,  H04W24/08 ,  H04W4/02 ,  H04B17/318

CPC classification number: G01C21/3453 ,  G01C21/3446 ,  H04B17/318 ,  H04W4/024 ,  H04W4/029 ,  H04W24/08

Abstract: Technologies for providing information to a user while traveling include a mobile computing device to determine network condition information associated with a route segment. The route segment may be one of a number of route segments defining at least one route from a starting location to a destination. The mobile computing device may determine a route from the starting location to the destination based on the network condition information. The mobile computing device may upload the network condition information to a crowdsourcing server. A mobile computing device may predict a future location of the device based on device context, determine a safety level for the predicted location, and notify the user if the safety level is below a threshold safety level. The device context may include location, time of day, and other data. The safety level may be determined based on predefined crime data. Other embodiments are described and claimed.

公开(公告)号：US10143421B2

公开(公告)日：2018-12-04

申请号：US14666618

申请日：2015-03-24

Applicant: INTEL CORPORATION

Inventor： John C. Weast ,  Glen J. Anderson ,  Giuseppe Raffa

IPC: H04B3/36 ,  A61B5/00 ,  G08B21/06 ,  A61B5/11

Abstract: A method is described to facilitate behavioral nudging. The method includes receiving sensory data from one or more wearable devices, determining a context for a user wearing the one or more wearable devices based on the sensory data, determining a mechanism to nudge the user to reinforce user behavior based on stored preferences and policies and transmitting a nudging stimulus to at least one of the wearable devices via the determined mechanism to provide a notification to the user.

公开(公告)号：US20180314249A1

公开(公告)日：2018-11-01

申请号：US15581124

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Mike B. Macpherson ,  Linda L. Hurd ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan

IPC: G05D1/00 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063

CPC classification number: G06F9/5016 ,  G06F9/5061

Abstract: A mechanism is described for facilitating storage management for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting one or more components associated with machine learning, where the one or more components include memory and a processor coupled to the memory, and where the processor includes a graphics processor. The method may further include allocating a storage portion of the memory and a hardware portion of the processor to a machine learning training set, where the storage and hardware portions are precise for implementation and processing of the training set.

公开(公告)号：US20180308203A1

公开(公告)日：2018-10-25

申请号：US15495081

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Joydeep Ray

IPC: G06T1/20 ,  G06N3/04 ,  H04L29/08

CPC classification number: G06T1/20 ,  G06F9/5061 ,  G06F9/5072 ,  G06N3/02 ,  G06N3/04 ,  H04L67/10

Abstract: A mechanism is described for facilitating sharing of data and compression expansion of models at autonomous machines. A method of embodiments, as described herein, includes detecting a first processor processing information relating to a neural network at a first computing device, where the first processor comprises a first graphics processor and the first computing device comprises a first autonomous machine. The method further includes facilitating the first processor to store one or more portions of the information in a library at a database, where the one or more portions are accessible to a second processor of a computing device.

公开(公告)号：US20180307983A1

公开(公告)日：2018-10-25

申请号：US15494948

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Narayan Srinivasa ,  Joydeep Ray ,  Nicolas C. Galoppo Von Borries ,  Ben Ashbaugh ,  Prasoonkumar Surti ,  Feng Chen ,  Barath Lakshmanan ,  Elmoustapha Ould-Ahmed-Vall ,  Liwei Ma ,  Linda L. Hurd ,  Abhishek R. Appu ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Chandrasekaran Sakthivel ,  Farshad Akhbari ,  Dukhwan Kim ,  Altug Koker ,  Nadathur Rajagopalan Satish

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06N3/04 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/082

Abstract: An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.