公开(公告)号：US20200334157A1

公开(公告)日：2020-10-22

申请号：US16919770

申请日：2020-07-02

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij Doshi

IPC: G06F12/0862

Abstract: Embodiments of the present disclosure relate to a controller that includes a monitor to determine an access pattern for a range of memory of a first computer memory device, and a pre-loader to pre-load a second computer memory device with a copy of a subset of the range of memory based at least in part on the access pattern, wherein the subset includes a plurality of cache lines. In some embodiments, the controller includes a specifier and the monitor determines the access pattern based at least in part on one or more configuration elements in the specifier. Other embodiments may be described and/or claimed.

公开(公告)号：US10795585B2

公开(公告)日：2020-10-06

申请号：US16015517

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Bhanu Shankar

IPC: G06F3/06 ,  G06F12/08

Abstract: An embodiment of a semiconductor apparatus may include technology to determine if a memory operation on a memory is avoidable, and suppress the memory operation if the memory operation is determined to be avoidable. Other embodiments are disclosed and claimed.

公开(公告)号：US10564972B1

公开(公告)日：2020-02-18

申请号：US16147066

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Vadim Sukhomlinov ,  Francesc Bernat Guim

IPC: G06F9/30 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0897

Abstract: An apparatus and method for efficiently reclaiming demoted cache lines. For example, one embodiment of a processor comprises: a cache hierarchy including at least one Level 1 (L1) cache and one or more lower level caches; a decoder to decode a cache line (CL) demote instruction specifying at least a first cache line; and execution circuitry to demote the first cache line responsive to the CL demote instruction, the execution circuitry to implement a writeback operation on the first cache line if the first cache line has been modified and homed in a specified memory tier or a default memory tier specified in a register.

公开(公告)号：US10528470B1

公开(公告)日：2020-01-07

申请号：US16006956

申请日：2018-06-13

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Bhanu Shankar

IPC: G06F12/00 ,  G06F12/0804 ,  G06F3/06

Abstract: In one embodiment, a processor has a core including at least one execution circuit, a retirement circuit, a first cache memory, and a first cache controller to control the first cache memory, where the first cache controller, in response to a store request to store a first value to a memory coupled to the processor, is to suppress the store operation when the first value matches a stored value of a cache line associated with the store operation. Other embodiments are described and claimed.

公开(公告)号：US10509912B2

公开(公告)日：2019-12-17

申请号：US15855791

申请日：2017-12-27

Applicant: INTEL CORPORATION

Inventor： Vadim Sukhomlinov ,  Tamir Damian Munafo ,  Kshitij Doshi

IPC: G06F21/60 ,  G06F21/62 ,  H04N5/235 ,  H04N5/238 ,  G06F21/83 ,  H04N5/225 ,  H04N5/232

Abstract: Techniques and apparatus for preventing unauthorized use of an image capture device are described. In one embodiment, for example, an apparatus may include an image capture unit operative to capture images from incident light incident on at least a portion of the image capture unit, a privacy assembly operative to prevent the image capture unit from generating a clear image responsive to a privacy active signal, and logic coupled to the privacy assembly, the logic to generate the privacy active signal responsive to the image capture unit being inactive. Other embodiments are described and claimed.

公开(公告)号：US10496536B2

公开(公告)日：2019-12-03

申请号：US16015880

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Bhanu Shankar

IPC: G06F12/0897 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/126 ,  G06F12/0868 ,  G06F12/0873

Abstract: In embodiments, an apparatus may include a CC, and a LLC coupled to the CC, the CC to reserve a defined portion of the LLC where data objects whose home location is in a NVM are given placement priority. In embodiments, the apparatus may be further coupled to at least one lower level cache and a second LLC, wherein the CC may further identify modified data objects in the at least one lower level cache whose home location is in a second NVM, and in response to the identification, cause the modified data objects to be written from the lower level cache to the second LLC, the second LLC located in a same socket as the second NVM.

公开(公告)号：US10481817B2

公开(公告)日：2019-11-19

申请号：US16022339

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Andreas Kleen ,  Harshad Sane

IPC: G06F3/06 ,  G06F9/50

Abstract: Methods, apparatus, systems and articles of manufacture to optimize dynamic memory assignments in multi-tiered memory systems are disclosed. An example computer readable storage medium comprises instructions to, during an offline profiling run of a computer application: responsive to a first malloc function call, perform a first backtrace to identify a first path preceding the first malloc function call and identify a size of a buffer in memory allocated to the first path; and determine an indicator corresponding to a temperature of the buffer allocated to the first path; and during runtime: responsive to a second malloc function call, perform a second backtrace to identify a second path preceding the second malloc function call; and responsive to the second path corresponding to the first path, allocate memory from a tier of memory based on the indicator.

公开(公告)号：US20190042124A1

公开(公告)日：2019-02-07

申请号：US16022339

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Andreas Kleen ,  Harshad Sane

IPC: G06F3/06

Abstract: Methods, apparatus, systems and articles of manufacture to optimize dynamic memory assignments in multi-tiered memory systems are disclosed. An example computer readable storage medium comprises instructions to, during an offline profiling run of a computer application: responsive to a first malloc function call, perform a first backtrace to identify a first path preceding the first malloc function call and identify a size of a buffer in memory allocated to the first path; and determine an indicator corresponding to a temperature of the buffer allocated to the first path; and during runtime: responsive to a second malloc function call, perform a second backtrace to identify a second path preceding the second malloc function call; and responsive to the second path corresponding to the first path, allocate memory from a tier of memory based on the indicator.

公开(公告)号：US20190042108A1

公开(公告)日：2019-02-07

申请号：US16015517

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Bhanu Shankar

IPC: G06F3/06

Abstract: An embodiment of a semiconductor apparatus may include technology to determine if a memory operation on a memory is avoidable, and suppress the memory operation if the memory operation is determined to be avoidable. Other embodiments are disclosed and claimed.

公开(公告)号：US20250071023A1

公开(公告)日：2025-02-27

申请号：US18453812

申请日：2023-08-22

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Francesc Guim Bernat ,  Ned Smith ,  Timothy Verrall ,  Rajesh Gadiyar

IPC: H04L41/0896 ,  H04L9/40 ,  H04L41/0893

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to manage telemetry data in an edge environment. An example apparatus includes a publisher included in a first edge platform to publish a wish list obtained from a consumer, the wish list including tasks to execute, a commitment determiner to determine whether a commitment is viable to execute at least one of the tasks in the wish list, the commitment to be processed to identify the telemetry data, and a communication interface to establish a communication channel to facilitate transmission of the telemetry data from the first edge platform to a second edge platform.