公开(公告)号：US20190044048A1

公开(公告)日：2019-02-07

申请号：US15891518

申请日：2018-02-08

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Lester Lampert ,  James S. Clarke ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Kanwaljit Singh ,  Roman Caudillo

IPC: H01L39/14 ,  H01L39/22 ,  H01L29/12 ,  H01L29/15 ,  H01L29/423 ,  H01L29/40 ,  H01L39/24 ,  G06N99/00

CPC classification number: H01L39/146 ,  G06N10/00 ,  H01L23/445 ,  H01L23/46 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L25/16 ,  H01L29/127 ,  H01L29/151 ,  H01L29/401 ,  H01L29/42316 ,  H01L39/228 ,  H01L39/24 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Disclosed herein are fabrication techniques for providing metal gates in quantum devices, as well as related quantum devices. For example, in some embodiments, a method of manufacturing a quantum device may include providing a gate dielectric over a qubit device layer, providing over the gate dielectric a pattern of non-metallic elements referred to as “gate support elements,” and depositing a gate metal on sidewalls of the gate support elements to form a plurality of gates of the quantum device.

公开(公告)号：US20190044046A1

公开(公告)日：2019-02-07

申请号：US16011829

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Roman Caudillo ,  Zachary R. Yoscovits ,  Lester Lampert ,  David J. Michalak ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  Hubert C. George ,  Nicole K. Thomas ,  James S. Clarke

IPC: H01L39/02 ,  H01L27/18 ,  H01L39/04 ,  H01L39/22 ,  H01L39/24 ,  G06N99/00

CPC classification number: H01L39/025 ,  G06N10/00 ,  H01L27/18 ,  H01L39/045 ,  H01L39/223 ,  H01L39/2493

Abstract: Various embodiments of the present disclosure present quantum circuit assemblies implementing vertically-stacked parallel-plate capacitors. Such capacitors include first and second capacitor plates which are parallel to one another and separated from one another by a gap measured along a direction perpendicular to the qubit plane, i.e. measured vertically. Fabrication techniques for manufacturing such capacitors are also disclosed. Vertically-stacked parallel-plate capacitors may help increasing coherence times of qubits, facilitate use of three-dimensional and stacked designs for quantum circuit assemblies, and may be particularly advantageous for realizing device scalability and use of 300-millimeter fabrication processes.

公开(公告)号：US20190043952A1

公开(公告)日：2019-02-07

申请号：US16018751

申请日：2018-06-26

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L23/46 ,  H01L29/78 ,  H01L29/43 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

公开(公告)号：US20190043822A1

公开(公告)日：2019-02-07

申请号：US15923346

申请日：2018-03-16

Applicant: Intel Corporation

Inventor： Javier A. Falcon ,  Ye Seul Nam ,  Adel A. Elsherbini ,  Roman Caudillo ,  James S. Clarke

IPC: H01L23/00 ,  H01L39/04 ,  H01L23/16

Abstract: Embodiments of the present disclosure describe novel qubit device packages, as well as related computing devices and methods. In one embodiment, an exemplary qubit device package includes a qubit die and a package substrate, where the qubit die is coupled to the package substrate using one or more preforms. In particular, a single preform may advantageously be used to replace a plurality of individual contacts, e.g. a plurality of individual solder bumps, electrically coupling the qubit die to the package substrate. Such packages may reduce design complexity and undesired coupling, and enable inclusion of larger numbers of qubits in a single qubit die.