公开(公告)号：US11955434B2

公开(公告)日：2024-04-09

申请号：US17861125

申请日：2022-07-08

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Eric J. Li ,  Shawna M. Liff ,  Javier A. Falcon ,  Joshua D. Heppner

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H01L25/16

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L25/04 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L24/16 ,  H01L25/042 ,  H01L25/071 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/112 ,  H01L25/115 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1436 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US20190042964A1

公开(公告)日：2019-02-07

申请号：US15925594

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Javier A. Falcon ,  Hubert C. George ,  Shawna M. Liff ,  James S. Clarke

IPC: G06N99/00 ,  B82Y10/00 ,  H01L29/66 ,  H01L23/31 ,  H01L23/00 ,  H01L29/12

CPC classification number: G06N10/00 ,  B82Y10/00 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/82 ,  H01L25/0652 ,  H01L29/127 ,  H01L29/66977

Abstract: Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include a plurality of dies electrically coupled to a package substrate, and lateral interconnects between different dies of the plurality of dies, wherein the lateral interconnects include a superconductor, and at least one of the dies of the plurality of dies includes quantum processing circuitry.

公开(公告)号：US10971453B2

公开(公告)日：2021-04-06

申请号：US16335845

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Johanna M. Swan ,  Shawna M. Liff ,  Henning Braunisch ,  Krishna Bharath ,  Javier Soto Gonzalez ,  Javier A. Falcon

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/03 ,  H01L23/498 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

公开(公告)号：US10256206B2

公开(公告)日：2019-04-09

申请号：US15923346

申请日：2018-03-16

Applicant: Intel Corporation

Inventor： Javier A. Falcon ,  Ye Seul Nam ,  Adel A. Elsherbini ,  Roman Caudillo ,  James S. Clarke

IPC: H01L23/00 ,  H01L39/04 ,  H01L23/16

Abstract: Embodiments of the present disclosure describe novel qubit device packages, as well as related computing devices and methods. In one embodiment, an exemplary qubit device package includes a qubit die and a package substrate, where the qubit die is coupled to the package substrate using one or more preforms. In particular, a single preform may advantageously be used to replace a plurality of individual contacts, e.g. a plurality of individual solder bumps, electrically coupling the qubit die to the package substrate. Such packages may reduce design complexity and undesired coupling, and enable inclusion of larger numbers of qubits in a single qubit die.

公开(公告)号：US09728425B1

公开(公告)日：2017-08-08

申请号：US15089491

申请日：2016-04-02

Applicant: INTEL CORPORATION

Inventor： Joshua D. Heppner ,  Serge Roux ,  Michael J. Baker ,  Javier A. Falcon

IPC: H01L21/56 ,  H01L21/67 ,  B29C35/08 ,  B29C70/84 ,  B29C70/80 ,  B29C70/88 ,  H01L23/31 ,  B29K63/00 ,  B29L31/34

CPC classification number: H01L21/563 ,  B29K2063/00 ,  B29K2995/0005 ,  B29L2031/3481 ,  H01L21/67126 ,  H01L23/3157 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/743 ,  H01L2224/92125

Abstract: Space-efficient underfilling techniques for electronic assemblies are described. According to some such techniques, an underfilling method may comprise mounting an electronic element on a surface of a substrate, dispensing an underfill material upon the surface of the substrate within a dispense region for forming an underfill for the electronic element, and projecting curing rays upon at least a portion of the dispensed underfill material to inhibit an outward flow of dispensed underfill material from the dispense region, and the underfill material may comprise a non-visible light (NVL)-curable material. Other embodiments are described and claimed.

公开(公告)号：US11335651B2

公开(公告)日：2022-05-17

申请号：US15773033

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georgios C. Dogiamis ,  Vijay K. Nair ,  Javier A. Falcon ,  Shawna M. Liff ,  Yoshihiro Tomita

IPC: H01L23/66 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L25/10 ,  H01L25/16

Abstract: Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

公开(公告)号：US11177912B2

公开(公告)日：2021-11-16

申请号：US15913026

申请日：2018-03-06

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Javier A. Falcon ,  Lester Lampert

IPC: H04L5/00 ,  G06N10/00

Abstract: One aspect of the present disclosure provides a quantum circuit assembly that includes a substrate with one or more qubit devices, and at least one demultiplexer included in a single chip with the qubit device(s). The demultiplexer is configured to receive a combined signal from external electronics, the combined signal including a combination of a plurality of signals in different frequency ranges, and to demultiplex said plurality of signals within the combined signal. The demultiplexer is further configured to apply different demultiplexed signals to different lines of a single qubit device, or/and to different qubit devices. Providing such demultiplexers on-chip with the qubit devices advantageously allows reducing the number of input/output lines coupling the chip with qubit devices and the external electronics.

公开(公告)号：US10380496B2

公开(公告)日：2019-08-13

申请号：US15925594

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Javier A. Falcon ,  Hubert C. George ,  Shawna M. Liff ,  James S. Clarke

IPC: G06N10/00 ,  B82Y10/00 ,  H01L29/12 ,  H01L23/00 ,  H01L29/66 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

Abstract: Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include a plurality of dies electrically coupled to a package substrate, and lateral interconnects between different dies of the plurality of dies, wherein the lateral interconnects include a superconductor, and at least one of the dies of the plurality of dies includes quantum processing circuitry.

公开(公告)号：US20190006572A1

公开(公告)日：2019-01-03

申请号：US15637682

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Javier A. Falcon ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Shawna M. Liff ,  Ye Seul Nam ,  James S. Clarke ,  Jeanette M. Roberts ,  Roman Caudillo

IPC: H01L39/04 ,  H01L25/16 ,  H01L23/538 ,  H01L23/66 ,  H01L23/552 ,  H01L39/02 ,  H01L39/24 ,  H01P3/08 ,  H01P11/00 ,  H05K1/02 ,  G06N99/00

Abstract: Disclosed herein are shielded interconnects, as well as related methods, assemblies, and devices. In some embodiments, a shielded interconnect may be included in a quantum computing (QC) assembly. For example, a QC assembly may include a quantum processing die; a control die; and a flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines.

公开(公告)号：US11296052B2

公开(公告)日：2022-04-05

申请号：US16639085

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Preston T. Meyers ,  Javier A. Falcon ,  Shawna M. Liff ,  Joe R. Saucedo ,  Adel A. Elsherbini ,  Albert S. Lopez ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L25/00

Abstract: A device package has substrates disposed on top of one another to form a stack, and pads formed on at least one of the top surface and the bottom surface of each of the substrates. The device package has interconnects electrically coupling at least one of the top surface and the bottom surface of each substrate to at least one of the top surface and the bottom surface of another substrate. The device package has pillars disposed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. The device package also has adhesive layers formed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates.