公开(公告)号：US20230397431A1

公开(公告)日：2023-12-07

申请号：US18204773

申请日：2023-06-01

Applicant: Micron Technology, Inc.

Inventor： Giorgio Servalli ,  Durai Vishak Nirmal Ramaswamy ,  Marcello Mariani

IPC: H10B53/20 ,  H10B53/10 ,  H01L23/522 ,  H01L23/528

CPC classification number: H10B53/20 ,  H10B53/10 ,  H01L23/5226 ,  H01L23/5283

Abstract: Methods, systems, and devices for formation for memory cells are described. A semiconductor device (e.g., a memory die) may include asymmetrical rows of conductive pillars and one or more dielectric materials. For example, the memory die may include a set of conductive pillars that are arranged in rows that are asymmetrically spaced. Here, a first row of conductive pillars may be a first distance away from a second row of conductive pillars and a second, larger distance away from a third row of conductive pillars. Additionally, the memory die may include one or more dielectric materials. In some cases, when depositing a dielectric material as part of a self-aligning process, the material may conformally line exposed surfaces according to a substantially uniform depth, which may decrease a subsequent quantity of masking operations to form the memory die.

公开(公告)号：US20230215947A1

公开(公告)日：2023-07-06

申请号：US18117483

申请日：2023-03-06

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Giorgio Servalli

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/51 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/516 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/78391

Abstract: Some embodiments include an integrated assembly having first and second pillars of semiconductor material laterally offset from one another. The pillars have source/drain regions and channel regions vertically offset from the source/drain regions. Gating structures pass across the channel regions, and extend along a first direction. An insulative structure is over regions of the first and second pillars, and extends along a second direction which is crosses the first direction. Bottom electrodes are coupled with the source/drain regions. Leaker-device-structures extend upwardly from the bottom electrodes. Ferroelectric-insulative-material is laterally adjacent to the leaker-device-structures and over the regions of the bottom electrodes. Top-electrode-material is over the ferroelectric-insulative-material and is directly against the leaker-device-structures. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230200048A1

公开(公告)日：2023-06-22

申请号：US17645348

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Giorgio Servalli ,  Marcello Mariani ,  Antonino Rigano ,  Marcello Calabrese

IPC: H01L27/108 ,  H01L25/065

CPC classification number: H01L27/10805 ,  H01L27/10882 ,  H01L27/10852 ,  H01L25/0655

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a pillar having an upper source/drain, a middle source/drain, a lower source/drain, an upper channel between the upper source/drain and the middle source/drain, and a lower channel between the middle source/drain and the lower source/drain. The integrated assembly includes a gate pair that includes a first gate and a second gate. The first gate is positioned on a first side of the pillar at a first height, and the second gate is positioned on a second side of the pillar, that is opposite the first side, at a second height that is different from the first height. The integrated assembly includes a capacitor that is electrically coupled with the upper source/drain. Some implementations include methods of forming the various structures, integrated assemblies, and memory devices.

公开(公告)号：US11557591B2

公开(公告)日：2023-01-17

申请号：US16855446

申请日：2020-04-22

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Giorgio Servalli

IPC: H01L27/108 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L21/306 ,  H01L29/78

Abstract: A method used in forming an array of memory cells comprises forming lines of top-source/drain-region material, bottom-source/drain-region material, and channel-region material vertically there-between in rows in a first direction. The lines are spaced from one another in a second direction. The top-source/drain-region material, bottom-source/drain-region material, and channel-region material have respective opposing sides. The channel-region material on its opposing sides is laterally recessed in the second direction relative to the top-source/drain-region material and the bottom-source/drain-region material on their opposing sides to form a pair of lateral recesses in the opposing sides of the channel-region material in individual of the rows. After the pair of lateral recesses are formed, the lines of the top-source/drain-region material, the channel-region material, and the bottom-source/drain-region material are patterned in the second direction to comprise pillars of individual transistors. Rows of wordlines are formed in the first direction that individually are operatively aside the channel-region material of individual of the pillars in the pairs of lateral recesses and that interconnect the transistors in that individual row. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20220190004A1

公开(公告)日：2022-06-16

申请号：US17680644

申请日：2022-02-25

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Giorgio Servalli

IPC: H01L27/13 ,  H01L21/84 ,  H01L27/12

Abstract: A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above insulator material. A mask is used to subtractively etch both the transistor material and thereafter the insulator material to form a plurality of pillars that individually comprise the transistor material and the insulator material. The insulator material is laterally-recessed from opposing lateral sides of individual of the pillars selectively relative to the transistor material of the individual pillars. The individual pillars are formed to comprise a first capacitor electrode that is in void space formed from the laterally recessing. Capacitors are formed that individually comprise the first capacitor electrode of the individual pillars. A capacitor insulator is aside the first capacitor electrode of the individual pillars and a second capacitor electrode is laterally-outward of the capacitor insulator. Vertical transistors are formed above the capacitors and individually comprise the transistor material of the individual pillars. Other aspects, including structure independent of method, are disclosed.

公开(公告)号：US20220173135A1

公开(公告)日：2022-06-02

申请号：US17107242

申请日：2020-11-30

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Giorgio Servalli

IPC: H01L27/13 ,  H01L21/84 ,  H01L27/12

Abstract: A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above insulator material. A mask is used to subtractively etch both the transistor material and thereafter the insulator material to form a plurality of pillars that individually comprise the transistor material and the insulator material. The insulator material is laterally-recessed from opposing lateral sides of individual of the pillars selectively relative to the transistor material of the individual pillars. The individual pillars are formed to comprise a first capacitor electrode that is in void space formed from the laterally recessing. Capacitors are formed that individually comprise the first capacitor electrode of the individual pillars. A capacitor insulator is aside the first capacitor electrode of the individual pillars and a second capacitor electrode is laterally-outward of the capacitor insulator. Vertical transistors are formed above the capacitors and individually comprise the transistor material of the individual pillars. Other aspects, including structure independent of method, are disclosed.

公开(公告)号：US20220020756A1

公开(公告)日：2022-01-20

申请号：US16933134

申请日：2020-07-20

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Giorgio Servalli

IPC: H01L27/11507 ,  H01L27/11504 ,  H01L23/60 ,  H01L49/02

Abstract: Some embodiments include an integrated assembly having a row of conductive posts. The conductive posts are spaced from one another by gaps. Leaker device material extends is within at least some of the gaps. An insulative material is along sidewalls of the conductive posts. A conductive structure is over the conductive posts. The conductive structure has downward projections extending into at least some of the gaps. The leaker device material is configured as segments along sides of the downward projections and extends from the sides to one or more of the conductive posts. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210391334A1

公开(公告)日：2021-12-16

申请号：US17460156

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Giorgio Servalli ,  Marcello Mariani

IPC: H01L27/108 ,  H01L27/11504 ,  H01L27/11507 ,  G11C11/22

Abstract: Some embodiments include an assembly having first and second pillars. Each of the pillars has an inner edge and an outer edge. A first gate is proximate a channel region of the first pillar. A second gate is proximate a channel region of the second pillar. A shield line is between the first and second pillars. First and second bottom electrodes are over the first and second pillars, respectively; and are configured as first and second angle plates. An insulative material is over the first and second bottom electrodes. The insulative material may be ferroelectric or non-ferroelectric. A top electrode is over the insulative material. Some embodiments include methods of forming assemblies.

公开(公告)号：US20210193210A1

公开(公告)日：2021-06-24

申请号：US17143800

申请日：2021-01-07

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Andrea Locatelli ,  Giorgio Servalli

IPC: G11C11/22 ,  G06F3/06

Abstract: Methods, systems, and devices for biasing techniques, such as open page biasing techniques, are described. A memory cell may be accessed during an access phase of an access operation, for example, an open page access operation. An activate pulse may be applied to the memory cell during the access phase. The memory cell may be biased to a non-zero voltage after applying the activate pulse and before a pre-charge phase. The pre-charge phase of the access phase may be initiated after biasing the memory cell to the non-zero voltage.

公开(公告)号：US20190237284A1

公开(公告)日：2019-08-01

申请号：US16375701

申请日：2019-04-04

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Giorgio Servalli

IPC: H01H85/06 ,  H01H85/11 ,  H01H85/08 ,  G11C13/00 ,  H01H37/32

CPC classification number: H01H85/06 ,  G11C13/0004 ,  H01H37/32 ,  H01H85/08 ,  H01H85/11 ,  Y10T29/49107

Abstract: Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive structure may be a titanium-containing structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Some embodiments include a method of forming and using a fuse. The fuse is formed to have a tungsten-containing structure directly contacting an electrically conductive structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Current exceeding the predetermined level is passed through the interface to rupture the interface.