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公开(公告)号：US09921898B1
公开(公告)日：2018-03-20
申请号：US15390833
申请日：2016-12-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael G. Miller , Ashutosh Malshe , Violante Moschiano , Peter Feeley , Gary F. Besinga , Sampath K. Ratnam , Walter Di-Francesco , Renato C. Padilla, Jr. , Yun Li , Kishore Kumar Muchherla
CPC classification number: G06F11/073 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/0751 , G06F11/0772 , G06F11/079
Abstract: Apparatus and methods of operating such apparatus include iteratively programming a group of memory cells to respective desired data states, wherein a particular memory cell is configured to store overhead data and a different memory cell is configured to store user data; determining whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, changing the desired data state of the particular memory cell before continuing with the programming. Apparatus and methods of operating such apparatus further include reading a data state of a particular memory cell of a last written page of memory cells, and marking the page as affected by power loss during a programming operation if the particular memory cell has any data state other than a particular data state.
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公开(公告)号：US09811258B2
公开(公告)日：2017-11-07
申请号：US14557682
申请日：2014-12-02
Applicant: Micron Technology, Inc.
Inventor： Neal A. Galbo , Peter Feeley , William H. Radke , Victor Y. Tsai , Robert N. Leibowitz
CPC classification number: G06F3/0604 , G06F3/0659 , G06F3/0683 , G06F13/1642
Abstract: The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device.
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公开(公告)号：US09767904B2
公开(公告)日：2017-09-19
申请号：US14455449
申请日：2014-08-08
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Koji Sakui , Peter Feeley
CPC classification number: G11C16/0408 , G11C16/0433 , G11C16/0483 , G11C16/10 , G11C16/26
Abstract: Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a three transistor memory cell device and a non-volatile memory device. Enable/disable gates enable selective access to the sense circuitry and page buffers by either the three transistor memory cell device or the non-volatile memory device.
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公开(公告)号：US20160203048A1
公开(公告)日：2016-07-14
申请号：US15059367
申请日：2016-03-03
Applicant: Micron Technology, Inc.
Inventor： Zhenlei Shen , William H. Radke , Peter Feeley
CPC classification number: G06F11/1068 , G06F11/1004 , G06F11/1048 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C29/04 , G11C29/52
Abstract: Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing.
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公开(公告)号：US09293213B2
公开(公告)日：2016-03-22
申请号：US14527416
申请日：2014-10-29
Applicant: Micron Technology, Inc.
Inventor： Koji Sakui , Peter Feeley
CPC classification number: G11C16/26 , G11C16/04 , G11C16/0483 , G11C16/06
Abstract: The present disclosure includes apparatuses and methods for sensing data stored in memory. A number of embodiments include an array of memory cells, and a controller coupled to the array and configured to sense a page of memory cells coupled to an activated access line by pre-charging only a single subset of a number of data lines coupled to the page, wherein more than two subsets of data lines are coupled to the page and the single subset is coupled to those memory cells storing at least a portion of a single sector of data of the page, and sensing the single subset of the number of data lines to determine the at least a portion of the single sector of data.
Abstract translation: 本公开包括用于感测存储在存储器中的数据的装置和方法。 许多实施例包括存储器单元的阵列，以及耦合到阵列的控制器，其被配置为通过仅对与多个数据线耦合的多个数据线的单个子集进行预充电来感测耦合到激活的接入线的存储器单元的页面 页面，其中多于两个的数据线子集耦合到页面，并且单个子集耦合到存储页面的单个数据扇区的至少一部分的那些存储器单元，并感测数据数量的单个子集 行以确定单个扇区数据的至少一部分。
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Patent Agency Ranking
公开(公告)号：US09269450B2
公开(公告)日：2016-02-23
申请号：US14327913
申请日：2014-07-10
Applicant: Micron Technology, Inc.
Inventor： William H. Radke , Zhenlei Shen , Peter Feeley
CPC classification number: G11C16/28 , G11C11/5642 , G11C16/0483 , G11C16/26
Abstract: The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.
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87.发明申请公开(公告)号：US20140355355A1
公开(公告)日：2014-12-04
申请号：US14327913
申请日：2014-07-10
Applicant: Micron Technology, Inc.
Inventor： William H. Radke , Zhenlei Shen , Peter Feeley
IPC: G11C16/28
CPC classification number: G11C16/28 , G11C11/5642 , G11C16/0483 , G11C16/26
Abstract: The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.
Abstract translation: 本公开包括用于调整设备中的感测电压的方法，设备和系统。 一个或多个实施例包括存储器单元和被配置为使用感测电压对存储器单元执行感测操作的控制器，以确定具有大于感测电压的阈值电压（Vt）的存储器单元的数量并且调整感测电压 用于至少部分地基于所确定的存储器单元的数量来确定存储器单元的状态。
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公开(公告)号：US20140233314A1
公开(公告)日：2014-08-21
申请号：US14182032
申请日：2014-02-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Zhenlei Shen , William H. Radke , Peter Feeley
CPC classification number: G06F11/1068 , G06F11/1004 , G06F11/1048 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C29/04 , G11C29/52
Abstract: Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing.
Abstract translation: 描述了用于存储器单元耦合补偿的方法和被配置为执行其的装置。 用于存储单元耦合补偿的一种或多种方法包括使用根据第一存储单元耦合补偿电压而改变的电压来确定存储单元的状态，对存储单元的状态执行错误检查，以及确定状态 使用响应于错误检查失败的根据第二存储器单元耦合补偿电压而改变的电压的存储器单元。
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公开(公告)号：US20140104951A1
公开(公告)日：2014-04-17
申请号：US13649886
申请日：2012-10-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Koji Sakui , Peter Feeley
CPC classification number: G11C16/26 , G11C16/04 , G11C16/0483 , G11C16/06
Abstract: The present disclosure includes apparatuses and methods for sensing data stored in memory. A number of embodiments include an array of memory cells, and a controller coupled to the array and configured to sense a page of memory cells coupled to an activated access line by pre-charging only a single subset of a number of data lines coupled to the page, wherein more than two subsets of data lines are coupled to the page and the single subset is coupled to those memory cells storing at least a portion of a single sector of data of the page, and sensing the single subset of the number of data lines to determine the at least a portion of the single sector of data.
Abstract translation: 本公开包括用于感测存储在存储器中的数据的装置和方法。 许多实施例包括存储器单元的阵列，以及耦合到阵列的控制器，其被配置为通过仅对与多个数据线耦合的多个数据线的单个子集进行预充电来感测耦合到激活的接入线的存储器单元的页面 页面，其中多于两个的数据线子集耦合到页面，并且单个子集耦合到存储页面的单个数据扇区的至少一部分的那些存储器单元，并感测数据数量的单个子集 行以确定单个扇区数据的至少一部分。
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公开(公告)号：US20240347128A1
公开(公告)日：2024-10-17
申请号：US18753389
申请日：2024-06-25
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Akira Goda , Dave Scott Ebsen , Lakshmi Kalpana Vakati , Jiangli Zhu , Peter Feeley , Sanjay Subbarao , Vivek Shivhare , Fangfang Zhu
CPC classification number: G11C29/52 , G11C29/022
Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.
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