公开(公告)号：US10983724B2

公开(公告)日：2021-04-20

申请号：US16132096

申请日：2018-09-14

Applicant: Micron Technology, Inc.

Inventor： Jiangli Zhu ,  Cheng Yuan Wu ,  Ying Yu Tai

IPC: G06F3/06

Abstract: A host operation to be performed can be received. Sub-operations that are associated with the received host operation can be determined. A memory component of multiple memory components can be identified for each sub-operation. Furthermore, each sub-operation can be transmitted to a media sequencer component that is associated with a respective memory component of the memory components.

公开(公告)号：US20210019085A1

公开(公告)日：2021-01-21

申请号：US16515699

申请日：2019-07-18

Applicant: Micron Technology, Inc.

Inventor： Jiangli Zhu ,  Ying Yu Tai

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

Abstract: A system controller of a memory system can present multiple physical functions (PFs) to a host computing system. The system controller can store commands from the host in separate queues and uses an arbiter circuit to issue commands. The arbiter can determine a difference value between a quota of commands and a count of commands issued from a respective queue. The quota is derived from a share specified by the host for the respective PF. The arbiter circuit determines a subset of queues by excluding queues that are empty and queues having a negative difference value. The arbiter circuit can randomly choose a selected queue from the subset and issue a command from the selected queue.

公开(公告)号：US20210019071A1

公开(公告)日：2021-01-21

申请号：US16916926

申请日：2020-06-30

Applicant: Micron Technology, Inc.

Inventor： Yueh-Hung Chen ,  Chih-Kuo Kao ,  Ying Yu Tai ,  Jiangli Zhu

IPC: G06F3/06 ,  G06F1/04

Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.

公开(公告)号：US20210019051A1

公开(公告)日：2021-01-21

申请号：US16916922

申请日：2020-06-30

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ying Yu Tai ,  Wei Wang

IPC: G06F3/06

Abstract: Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can receive a first command for performing an operation on a set of management units. The acceleration engine can generate a set of one or more second commands to perform the operation on each management unit of the set of management units based on receiving the first command. The acceleration engine can perform the operation on each management unit of the set of management units based on generating the set of second commands.

公开(公告)号：US20210011658A1

公开(公告)日：2021-01-14

申请号：US16510567

申请日：2019-07-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ying Yu Tai ,  Jiangli Zhu

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22

Abstract: A request can be received to perform a read operation to retrieve data at a memory sub-system. A time to perform the read operation can be determined. A time a write operation was performed to store the data at the memory sub-system can be determined. An amount of time that has elapsed since the time the performance of the write operation until the time to perform the read operation can be determined. A read voltage from a plurality of read voltages can be selected based on the amount of time that has elapsed. The read operation can be performed to retrieve the data by using the read voltage.

公开(公告)号：US10891224B2

公开(公告)日：2021-01-12

申请号：US16123979

申请日：2018-09-06

Applicant: Micron Technology, Inc.

Inventor： Ning Chen ,  Jiangli Zhu ,  Ying Yu Tai

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/02 ,  G06F3/06

Abstract: A determination is made that a source group of data management units of a memory component satisfies a threshold wear condition. A wear leveling operation is performed by copying data from a first data management unit of the source group of data management units to a second data management unit of a destination group of data management units of the memory component. A logical address of the first data management unit is determined. Indicators in a mapping data structure are moved from entries associated with the first data management unit to another entries in the mapping data structure that are subsequent to the entries associated with the first data management unit. The indicators are used to access data requested by a host system at the source group of data management units or at the destination group of data management units.

公开(公告)号：US10860219B2

公开(公告)日：2020-12-08

申请号：US16153016

申请日：2018-10-05

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ning Chen ,  Ying Yu Tai

IPC: G06F3/06 ,  G06F12/10

Abstract: Data is copied, from a second group of data blocks in a second plurality of groups of data blocks that are mapped, to a first group of data blocks in a first set of groups of data blocks that are not mapped to include the first group of data blocks in the second set of groups of data blocks that are mapped. A sub-total write counter associated with the first group of data blocks is reset. A value of the sub-total write counter indicates a number of write operations performed on the first group of data blocks since the first group of data blocks has been included in the second set of groups of data blocks. A wear leveling operation is performed on the first group of data blocks based on the sub-total write counter.

公开(公告)号：US20200334137A1

公开(公告)日：2020-10-22

申请号：US16921479

申请日：2020-07-06

Applicant: Micron Technology, Inc.

Inventor： Ying Yu Tai ,  Jiangli Zhu

IPC: G06F12/02 ,  G06F12/06

Abstract: A system includes a memory device and a processing device, coupled to the memory device. The processing device is to sample a first subset of data units from a set of data units of the memory device using a biased sampling process that increases a probability of sampling particular data units from the set of data units based on one or more characteristics associated with the particular data units. The processing device is to identify a first candidate data unit from the first subset of data units and perform a wear leveling operation in view of the first candidate data unit.

公开(公告)号：US20200294608A1

公开(公告)日：2020-09-17

申请号：US16889736

申请日：2020-06-01

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ying Yu Tai

IPC: G11C16/34 ,  G11C13/00 ,  G11C29/52 ,  G11C11/406

Abstract: One or more write operations are performed on a memory component. A determination is made as to whether a number of the plurality of write operations performed on the memory component since performance of a refresh operation on the memory component exceeds a threshold value. In response to determining that the number of write operations performed on the memory component exceeds the threshold value, a memory cell of the memory component is identified based on the plurality of write operations. Data stored at memory cells of the memory component that are proximate to the identified memory cell is refreshed.

公开(公告)号：US20200278808A1

公开(公告)日：2020-09-03

申请号：US16289053

申请日：2019-02-28

Applicant: Micron Technology, Inc.

Inventor： Jiangli Zhu ,  Wei Wang ,  Ying Yu Tai ,  Jason Duong ,  Chih-Kuo Kao

IPC: G06F3/06

Abstract: A processing device in a memory system provides an execution grant to a first queue of a plurality of queues, the first queue storing a first plurality of memory commands to be executed on the memory component. The processing device further determines whether a number of commands from the first queue that have been executed since the first queue received the execution grant satisfies an executed transaction threshold criterion and whether a number of pending commands in a second queue of the plurality of queues satisfies a promotion threshold criterion, the second queue storing a second plurality of memory commands to be executed on the memory component. Responsive to at least one of the executed transaction threshold criterion or the promotion threshold criterion being satisfied, the processing device provides the execution grant to the second queue.