公开(公告)号：US11620197B2

公开(公告)日：2023-04-04

申请号：US17392133

申请日：2021-08-02

Applicant: PURE STORAGE, INC.

Inventor： John D. Davis ,  John Hayes ,  Hari Kannan ,  Nenad Miladinovic ,  Zhangxi Tan

IPC: G06F11/10 ,  G06F11/20 ,  G06F11/16 ,  G06F3/06

Abstract: A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.

公开(公告)号：US20230024480A1

公开(公告)日：2023-01-26

申请号：US17955493

申请日：2022-09-28

Applicant: Pure Storage, Inc.

Inventor： Hari Kannan ,  Gordon James Coleman ,  Yijie Zhao ,  Peter E. Kirkpatrick ,  Robert Lee ,  Yuhong Mao ,  Boris Feigin

IPC: G06F3/06 ,  G06F11/34

Abstract: One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.

公开(公告)号：US11544143B2

公开(公告)日：2023-01-03

申请号：US17213734

申请日：2021-03-26

Applicant: Pure Storage, Inc.

Inventor： John D. Davis ,  John Hayes ,  Zhangxi Tan ,  Hari Kannan ,  Nenad Miladinovic

IPC: G06F11/10 ,  H03M13/37 ,  H03M13/11 ,  H03M13/00 ,  H03M13/35 ,  H03M13/15

Abstract: A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable.

公开(公告)号：US20220404970A1

公开(公告)日：2022-12-22

申请号：US17897014

申请日：2022-08-26

Applicant: Pure Storage, Inc.

Inventor： John D. Davis ,  John Hayes ,  Hari Kannan ,  Nenad Miladinovic ,  Zhangxi Tan

IPC: G06F3/06 ,  G06F11/10 ,  H03M13/37 ,  G11C29/52 ,  H03M13/15

Abstract: A storage system is provided. The storage system includes a plurality of non-volatile memory units and a processor operatively coupled to a plurality of non-volatile memory units. The processor is to perform a method including receiving a request to read data from the storage system. The method also includes determining whether a storage operation should be delayed, based on the request to read the data from the storage system. The method further includes in response to determining that the storage operation should be delayed, delaying the storage operation. The method further includes performing a read operation for the request to read the data.

公开(公告)号：US11436023B2

公开(公告)日：2022-09-06

申请号：US16383465

申请日：2019-04-12

Applicant: Pure Storage, Inc.

Inventor： Russell Sears ,  Hari Kannan ,  Yuhong Mao

IPC: G06F9/44 ,  G06F9/4401 ,  G06F3/06 ,  G06F12/02 ,  G06F16/907 ,  G06F12/1009

Abstract: A method of operating a storage system is provided. The method includes executing an operating system on one or more processors of a compute device that is coupled to one or more solid-state drives and executing a file system on the one or more processors of the compute device. The method includes configuring the compute device with one or more replaceable plug-ins that are specific to the one or more solid-state drives, and executing a flash translation layer on the one or more processors of the compute device, with assistance through the one or more replaceable plug-ins for reading and writing the one or more solid-state drives.

公开(公告)号：US11416338B2

公开(公告)日：2022-08-16

申请号：US16857475

申请日：2020-04-24

Applicant: PURE STORAGE, INC.

Inventor： Hari Kannan ,  Nenad Miladinovic

IPC: G06F12/00 ,  G06F11/10 ,  G06F11/20 ,  G06F12/02

Abstract: A storage system has a resiliency scheme to enhance storage system performance. The storage system composes a RAID stripe. The storage system mixes an ordering of portions of the RAID stripe, based on reliability differences across portions of the solid-state memory. The storage system writes the mixed ordering RAID stripe across the solid-state memory.

公开(公告)号：US11409437B2

公开(公告)日：2022-08-09

申请号：US16999381

申请日：2020-08-21

Applicant: Pure Storage, Inc.

Inventor： Hari Kannan ,  Robert Lee

IPC: G06F3/06 ,  G06F8/654 ,  G06F8/65 ,  G06F11/14 ,  G06F12/02

Abstract: A method for non-disruptive upgrade of a storage system is provided. The method includes disabling, by an interlock, access by one or more processors of the storage system to the first memory, responsive to a request. The method includes persisting configuration information in the first memory to the solid-state memory, with the access to the first memory disabled by the interlock, wherein the persisting, the first memory and the solid-state memory are supported by an energy reserve. The method includes enabling, by the interlock, access by the one or more processors to the first memory, responsive to completing the persisting, and writing, by the one or more processors of the storage system, to the first memory, to perform the upgrade with further configuration information, with the access enabled by the interlock and wherein at least the persisting is accomplished without power cycling.

公开(公告)号：US11328767B2

公开(公告)日：2022-05-10

申请号：US17085362

申请日：2020-10-30

Applicant: Pure Storage, Inc.

Inventor： Hari Kannan ,  Peter E. Kirkpatrick

IPC: G11C11/00 ,  G11C11/56 ,  G11C16/10 ,  G06F3/06 ,  G06F12/02

Abstract: A method for page writes for triple or higher level cell flash memory is provided. The method includes receiving data in a storage system, from a client that is agnostic of page write requirements for triple or higher level cell flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The method includes accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple or higher level cell flash memory in the storage system. The method includes writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or the higher level cell, flash memory in the storage system as an atomic write.

公开(公告)号：US11289169B2

公开(公告)日：2022-03-29

申请号：US16845916

申请日：2020-04-10

Applicant: Pure Storage, Inc.

Inventor： Hari Kannan ,  Robert Lee ,  Yuhong Mao

IPC: G06F11/00 ,  G11C16/34 ,  G11C11/402 ,  G01R31/317 ,  G06F11/07 ,  H04L1/20 ,  G06F11/10 ,  G11C16/04

Abstract: A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

公开(公告)号：US20220092025A1

公开(公告)日：2022-03-24

申请号：US17543484

申请日：2021-12-06

Applicant: PURE STORAGE, INC.

Inventor： Sankara Vaideeswaran ,  Hari Kannan ,  Gordon James Coleman

IPC: G06F16/11 ,  G06F16/182 ,  G06F9/48 ,  G06F11/30

Abstract: A priority queue including an order of local data relocation operations to be performed by a plurality of solid-state storage devices is maintained. An indication of a new local data relocation operation is received from a solid-state storage device of the plurality of solid-state storage devices for data stored at the solid-state storage device, the indication including information associated with the data. The new local data relocation operation is inserted into a position in the order of the priority queue based on the information associated with the data.