公开(公告)号：US20240204039A1

公开(公告)日：2024-06-20

申请号：US18067557

申请日：2022-12-16

Applicant: QUALCOMM Incorporated

Inventor： Kai LIU ,  Jui-Yi CHIU ,  Jonghae KIM

IPC: H01L23/528 ,  H01L23/522 ,  H05K1/11 ,  H05K1/16

CPC classification number: H01L28/10 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5283 ,  H05K1/115 ,  H05K1/165 ,  H05K2201/0215

Abstract: Disclosed is a device including an inductor that includes a substrate; a plurality of vias disposed through the substrate and filled with a conductive metal; a via structure disposed through the substrate and extending between the plurality of vias, wherein the via structure is filled with a magnetic material to form a magnetic core of the inductor; and one or more patterned metallization layers interconnecting the conductive metal of the plurality of vias; wherein the one or more patterned metallization layers and the conductive metal filling the plurality of vias form a winding of the inductor about the magnetic core.

公开(公告)号：US20240203895A1

公开(公告)日：2024-06-20

申请号：US18067565

申请日：2022-12-16

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Ranadeep DUTTA

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L21/566 ,  H01L21/568 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/0655 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2924/14215 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/2027 ,  H01L2924/3025

Abstract: Disclosed are examples of multi-die modules that includes a die (e.g., a power amplifier) and an adjacent die placed side-by-side and bonded onto a substrate with a mold compound. The die (e.g., a switch or a low noise amplifier) may be double EMI shielded to minimize or even eliminate EMI/noise coupling with the adjacent die (e.g., switch, low noise amplifier, etc.). Another mold compound, which can be thermally conductive, may be provided to improve transfer of heat away from the die and/or the adjacent die.

公开(公告)号：US20240105797A1

公开(公告)日：2024-03-28

申请号：US17934400

申请日：2022-09-22

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Haining YANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  George Pete IMTHURN

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed are apparatuses including transistor and methods for fabricating the same. The transistor may include a drain substantially enclosed in a drain silicide layer, wherein an integral drain via portion of the drain silicide layer is coupled to a second drain contact and wherein a first drain via couples the drain silicide layer to a first drain contact. The transistor may include a source substantially enclosed in a source silicide layer, wherein an integral source via portion of the source silicide layer is coupled to a second source contact and wherein a first source via couples the source silicide layer to a first source contact. The transistor may include a gate disposed between the source and the drain.

公开(公告)号：US20230260947A1

公开(公告)日：2023-08-17

申请号：US18303345

申请日：2023-04-19

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM ,  Abdolreza LANGARI

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L24/29 ,  H01L24/27 ,  H01L23/3157 ,  H01L21/565 ,  H01L23/481 ,  H01L2924/01014 ,  H01L2924/1205 ,  H01L2924/14

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly.

公开(公告)号：US20230187106A1

公开(公告)日：2023-06-15

申请号：US17643685

申请日：2021-12-10

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Sang-June PARK ,  Je-Hsiung LAN ,  Ranadeep DUTTA

IPC: H01C7/00

CPC classification number: H01C7/006

Abstract: Disclosed is a sheet resistor designed to operate in a high frequency environment. Unlike conventional sheet resistors, the equivalent series inductance (ESL) is minimized or even eliminated altogether when using the designed sheet resistor. As a result, better signal isolation can be achieved.

公开(公告)号：US20220415808A1

公开(公告)日：2022-12-29

申请号：US17357811

申请日：2021-06-24

Applicant: QUALCOMM Incorporated

Inventor： Bharani CHAVA ,  Abinash ROY ,  Stanley Seungchul SONG ,  Jonghae KIM

IPC: H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

Abstract: A package comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

公开(公告)号：US20220352359A1

公开(公告)日：2022-11-03

申请号：US17244293

申请日：2021-04-29

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Jonghae KIM ,  Je-Hsiung LAN

IPC: H01L29/737 ,  H01L29/205 ,  H01L29/66 ,  H01L23/498 ,  H01L23/14 ,  H01L23/00

Abstract: In an aspect, a heterojunction bipolar transistor (HBT) includes a sub-collector disposed on a collector. The collector has a collector contact disposed on the sub-collector and located on a first side of the heterojunction bipolar transistor. The HBT includes an emitter disposed on an emitter cap. The emitter has an emitter contact disposed on the emitter cap and located on a second side of the heterojunction bipolar transistor. The HBT includes a base having a base contact located on the second side of the heterojunction bipolar transistor.

公开(公告)号：US20220223585A1

公开(公告)日：2022-07-14

申请号：US17144411

申请日：2021-01-08

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H01L27/08 ,  H01L25/10 ,  H01L49/02

Abstract: Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.

公开(公告)号：US20220084922A1

公开(公告)日：2022-03-17

申请号：US17323249

申请日：2021-05-18

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Jinseong KIM

IPC: H01L23/498 ,  H01L23/64 ,  H01L21/48

Abstract: An integrated circuit (IC) package includes a chip. The chip has a front-side surface and a backside surface, opposite the front-side surface. The front-side surface of the chip includes a plurality of bump sites. The integrated circuit package also includes a plurality of dies. Each of the plurality of dies are composed of integrated passive devices. The plurality of dies have conformal die edge patterns to enable placement of a front-side surface of each of the plurality of dies on predetermined portions of the plurality of bumps sites on the front-side surface of the chip.

公开(公告)号：US20220022315A1

公开(公告)日：2022-01-20

申请号：US16929004

申请日：2020-07-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Jonghae KIM ,  Periannan CHIDAMBARAM

IPC: H05K1/11 ,  G06F1/18 ,  H05K1/02 ,  H05K3/10 ,  H05K3/40

Abstract: An integrated circuit (IC) package is described. The IC package includes a metallization structure. The IC package also includes a first die in a package substrate layer. The package substrate includes a first surface and a second surface, opposite the first surface. The second surface of the package substrate layer is on the metallization structure. The IC package further includes a second die on the first surface of the package substrate layer and on the first die. The IC package also includes through vias in the package substrate layer to couple pads of the second die to metal routing layers at a first surface of the metallization structure. The IC package further includes package bumps on a second surface of the metallization structure, opposite the first surface, and coupled to the pads of the second die through the metal routing layers.