公开(公告)号：US11626502B2

公开(公告)日：2023-04-11

申请号：US17398363

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin Shin ,  Sangwon Kim ,  Kyung-Eun Byun ,  Hyunjae Song ,  Keunwook Shin ,  Eunkyu Lee ,  Changseok Lee ,  Yeonchoo Cho ,  Taejin Choi

IPC: H01L29/45 ,  H01L29/40 ,  H01L29/15 ,  H01L27/108

Abstract: An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of a peripheral region of the semiconductor layer, a metal layer facing the semiconductor layer, a graphene layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the graphene layer and the semiconductor and covering the first region.

公开(公告)号：US11575011B2

公开(公告)日：2023-02-07

申请号：US17515713

申请日：2021-11-01

Applicant: Samsung Electronics Co., Ltd. ,  THE UNIVERSITY OF CHICAGO ,  Center for Technology Licensing at Cornell University

Inventor： Minhyun Lee ,  Jiwoong Park ,  Saien Xie ,  Jinseong Heo ,  Hyeonjin Shin

IPC: H01L29/15 ,  H01L29/10

Abstract: Provided are a superlattice structure including a two-dimensional material and a device including the superlattice structure. The superlattice structure may include at least two different two-dimensional (2D) materials bonded to each other in a lateral direction, and an interfacial region of the at least two 2D materials may be strained. The superlattice structure may have a bandgap adjusted by the interfacial region that is strained. The at least two 2D materials may include first and second 2D materials. The first 2D material may have a first bandgap in an intrinsic state thereof. The second 2D material may have a second bandgap in an intrinsic state thereof. An interfacial region of the first and second 2D materials and an adjacent region may have a third bandgap between the first bandgap and the second bandgap.

公开(公告)号：US11532709B2

公开(公告)日：2022-12-20

申请号：US17203010

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Minsu Seol ,  Yeonchoo Cho ,  Hyeonjin Shin

IPC: H01L29/10 ,  H01L29/24 ,  H01L29/423

Abstract: A field effect transistor includes a substrate, a source electrode and a drain electrode on the substrate and apart from each other in a first direction, a plurality of channel layers, a gate insulating film surrounding each of the plurality of channel layers, and a gate electrode surrounding the gate insulating film. Each of the plurality of channel layers has ends contacting the source electrode and the drain electrode. The plurality of channel layers are spaced apart from each other in a second direction away from the substrate. The plurality of channel layers include a 2D semiconductor material.

公开(公告)号：US11476117B2

公开(公告)日：2022-10-18

申请号：US16928560

申请日：2020-07-14

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Kyung-Eun Byun ,  Hyoungsub Kim ,  Taejin Park ,  Hoijoon Kim ,  Hyeonjin Shin ,  Wonsik Ahn ,  Mirine Leem ,  Yeonchoo Cho

IPC: H01L21/02

Abstract: A method of forming a transition metal dichalcogenide thin film on a substrate includes treating the substrate with a metal organic material and providing a transition metal precursor and a chalcogen precursor around the substrate to synthesize transition metal dichalcogenide on the substrate. The transition metal precursor may include a transition metal element and the chalcogen precursor may include a chalcogen element.

公开(公告)号：US11462477B2

公开(公告)日：2022-10-04

申请号：US17082494

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeonjin Shin ,  Minhyun Lee ,  Changseok Lee ,  Hyeonsuk Shin ,  Seokmo Hong

IPC: H01L23/532 ,  H01L23/522

Abstract: An interconnect structure and an electronic apparatus including the interconnect structure are provided. The interconnect structure includes a conductive layer; a dielectric layer configured to surround at least a part of the conductive layer; and a diffusion barrier layer disposed between the conductive layer and the dielectric layer and configured to limit and/or prevent a conductive material of the conductive layer from diffusing into the dielectric layer, and at least one of the dielectric layer and the diffusion barrier layer includes a boron nitride layer of a low dielectric constant.

公开(公告)号：US11431265B2

公开(公告)日：2022-08-30

申请号：US17007035

申请日：2020-08-31

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyungeun Byun ,  Jaeyoung Kim ,  Minsu Seol ,  Hyeonjin Shin ,  Jeongmin Baik ,  Woojung Yang ,  Byeonguk Ye ,  Jaewon Lee ,  Jinpyo Lee ,  Kyeongnam Kim

IPC: H02N1/04

Abstract: A triboelectric generator includes a first electrode and a second electrode spaced apart from each other, a first charging part on the first electrode, a second charging part on the second electrode, and a grounding unit. The first charging part and the second charging part may be configured to contact each other through a sliding motion. The grounding unit may be configured to intermittently connect a charge reservoir to the second charging part. The grounding unit may be configured to vary the electric potential of the second charging part so as to amplify current flowing between electrodes of the triboelectric generator.

公开(公告)号：US11424186B2

公开(公告)日：2022-08-23

申请号：US17082530

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeonjin Shin ,  Minhyun Lee ,  Changseok Lee ,  Kyung-Eun Byun ,  Hyeonsuk Shin ,  Seokmo Hong

IPC: H01L23/532 ,  H01L23/522 ,  H01L27/108

Abstract: A semiconductor memory device and a device including the same are provided. The semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines in a second direction crossing the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer.

公开(公告)号：US20220077154A1

公开(公告)日：2022-03-10

申请号：US17318563

申请日：2021-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Huijung Kim ,  Minwoo Kwon ,  Sangyeon Han ,  Sangwon Kim ,  Junsoo Kim ,  Hyeonjin Shin ,  Eunkyu Lee

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

公开(公告)号：US11086223B2

公开(公告)日：2021-08-10

申请号：US16426046

申请日：2019-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin Shin ,  Sangwon Kim ,  Minsu Seol ,  Seongjun Park ,  Yeonchoo Cho

IPC: G03F7/36 ,  G03F7/11 ,  G03F7/09 ,  G03F7/16

Abstract: A hardmask composition may include graphene nanoparticles having a size in a range of about 5 nm to about 100 nm and a solvent.

公开(公告)号：US11034847B2

公开(公告)日：2021-06-15

申请号：US15944920

申请日：2018-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Seol ,  Sangwon Kim ,  Hyeonjin Shin ,  Dongwook Lee ,  Seongjun Park ,  Yunseong Lee ,  Seongjun Jeong ,  Alum Jung

IPC: C09D7/63 ,  G03F7/11 ,  G03F7/09 ,  G03F7/07 ,  G03F7/40 ,  C07F3/02 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  G03F7/38 ,  H01L21/311 ,  H01L21/3213 ,  G03F7/075

Abstract: Provided are a hardmask composition including a structure represented by Formula 1 and a solvent, a method of forming a pattern using the hardmask composition, and a hardmask formed from the hardmask composition. wherein in Formula 1, R1 to R8, X, and M are described in detail in the detailed description.