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    Optimum cache access scheme for multi endpoint atomic access in a multicore system
    86.
    发明授权
    Optimum cache access scheme for multi endpoint atomic access in a multicore system 有权
    用于多核系统中多端点原子访问的最佳缓存访问方案

    公开(公告)号：US09372796B2

    公开(公告)日：2016-06-21

    申请号：US14061494

    申请日：2013-10-23

    Applicant: Texas Instruments Incorporated

    Inventor： Kai Chirca ,  Matthew D Pierson

    IPC: G06F12/00 ,  G06F12/08 ,  G06F13/16 ,  G06F13/00

    CPC classification number: G06F12/0815 ,  G06F12/0862 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/1684

    Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. The two consecutive slots assigned per cache line access are always in the same direction for maximum access rate.

    Abstract translation: 描述的MSMC（多核共享存储器控制器）是一种旨在管理多处理器内核，其他母盘外设或DMA之间流量的模块，以及多核SoC中的EMIF（外部存储器间隔）。 本发明在仲裁事务之前统一属于从属方的所有事务大小，以便降低仲裁过程的复杂性，并在所有主机之间提供最佳的带宽管理。 每个高速缓存行访问分配的两个连续插槽总是处于相同的方向，以获得最大访问速率。

    Multicore Bus Architecture With Non-Blocking High Performance Transaction Credit System
    87.
    发明申请
    Multicore Bus Architecture With Non-Blocking High Performance Transaction Credit System 有权
    具有非阻塞性高性能交易信用系统的多核总线架构

    公开(公告)号：US20160124883A1

    公开(公告)日：2016-05-05

    申请号：US14530203

    申请日：2014-10-31

    Applicant: Texas Instruments Incorporated

    Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

    IPC: G06F13/40 ,  G06F13/42 ,  G06F13/364

    CPC classification number: G06F13/404 ,  G06F13/364 ,  G06F13/42 ,  G06F13/4282 ,  H04L47/10 ,  H04L47/215 ,  H04L47/39

    Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

    Abstract translation: 本发明是总线通信协议。 主设备存储总线信用。 主设备只有在拥有足够数量和类型的总线信用时才可以传输总线事务。 在传输时，主设备减少存储的总线信用的数量。 总线信用量对应于从设备上用于接收总线事务的资源。 如果伴随着适当的信用，从设备必须接收总线交易。 从设备为事务提供服务。 然后从设备传送信用回报。 主设备将相应的信用数量和类型添加到存储量。 从设备准备接受另一个总线事务，并且主设备被重新启用以启动总线事务。 在许多类型的交互中，根据进程的状态，总线代理可以充当主机和从机。

    OPTIONAL ACKNOWLEDGEMENT FOR OUT-OF-ORDER COHERENCE TRANSACTION COMPLETION
    90.
    发明申请
    OPTIONAL ACKNOWLEDGEMENT FOR OUT-OF-ORDER COHERENCE TRANSACTION COMPLETION 审中-公开
    用于不及格相关交易完成的可选确认

    公开(公告)号：US20150370710A1

    公开(公告)日：2015-12-24

    申请号：US14841956

    申请日：2015-09-01

    Applicant: Texas Instruments Incorporated

    Inventor： Daniel B. Wu ,  Matthew D. Pierson ,  Kai Chirca ,  Timothy D. Anderson

    IPC: G06F12/08

    CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

    Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

    Abstract translation: 为了能够有效跟踪事务，使用确认期望信号来给缓存一致互连提供一个交易是否需要连贯的所有权跟踪的提示。 该信号通知高速缓存相干互连，以便在读/写传输完成时期望来自发起主机的所有权转移确认信号。 因此，高速缓存相干互连可以在其一致性点继续跟踪事务，直到在必要时从发起主机接收到确认。

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