公开(公告)号：US09281367B2

公开(公告)日：2016-03-08

申请号：US14697615

申请日：2015-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Chieh-Te Chen

IPC: H01L29/772 ,  H01L29/417 ,  H01L21/768 ,  H01L29/78 ,  H01L23/485 ,  H01L29/66 ,  H01L21/283 ,  H01L21/321 ,  H01L23/528 ,  H01L29/45 ,  H01L23/532 ,  H01L29/165

CPC classification number: H01L21/76897 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.

公开(公告)号：US20150357431A1

公开(公告)日：2015-12-10

申请号：US14831881

申请日：2015-08-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L29/66 ,  H01L21/768

CPC classification number: H01L29/665 ,  H01L21/76814 ,  H01L21/76879 ,  H01L29/41791 ,  H01L29/66515 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/785

Abstract: The present invention provides a manufacturing method of a semiconductor structure, comprising the following steps. First, a substrate is provided, a first dielectric layer is formed on the substrate, a metal gate is disposed in the first dielectric layer and at least one source/drain region (S/D region) is disposed on two sides of the metal gate, a second dielectric layer is then formed on the first dielectric layer, a first etching process is then performed to form a plurality of first trenches in the first dielectric layer and the second dielectric layer, wherein the first trenches expose each S/D region. Afterwards, a salicide process is performed to form a salicide layer in each first trench, a second etching process is then performed to form a plurality of second trenches in the first dielectric layer and the second dielectric layer, and the second trenches expose the metal gate.

Abstract translation: 本发明提供一种半导体结构的制造方法，包括以下步骤。 首先，提供基板，在基板上形成第一介电层，金属栅极设置在第一介电层中，并且至少一个源极/漏极区（S / D区）设置在金属栅极的两侧 然后在第一介电层上形成第二电介质层，然后执行第一蚀刻工艺以在第一电介质层和第二电介质层中形成多个第一沟槽，其中第一沟槽暴露每个S / D区域。 然后，进行自对准处理以在每个第一沟槽中形成自对准硅化物层，然后执行第二蚀刻工艺以在第一介电层和第二介电层中形成多个第二沟槽，并且第二沟槽暴露金属栅极 。

公开(公告)号：US20150243663A1

公开(公告)日：2015-08-27

申请号：US14187628

申请日：2014-02-24

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Jia-Rong Wu ,  Ching-Ling Lin

IPC: H01L27/092 ,  H01L29/417 ,  H01L21/02 ,  H01L29/45 ,  H01L21/8238 ,  H01L21/285

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/41791

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a dual silicide approach of the embodiment, a substrate having a first area with plural first metal gates and a second area with plural second metal gates is provided, wherein the adjacent first metal gates and the adjacent second metal gates are separated by an insulation. A dielectric layer is formed on the first and second metal gates and the insulation. The dielectric layer and the insulation at the first area are patterned by a first mask to form a plurality of first openings. Then, a first silicide is formed at the first openings. The dielectric layer and the insulation at the second area are patterned by a second mask to form a plurality of second openings. Then, a second silicide is formed at the second openings.

Abstract translation: 提供一种制造半导体器件的方法和使用其制造的器件。 根据本实施例的双硅化物方法，提供了具有多个第一金属栅极的第一区域和具有多个第二金属栅极的第二区域的基板，其中相邻的第一金属栅极和相邻的第二金属栅极被绝缘体 。 在第一和第二金属栅极和绝缘体上形成电介质层。 介电层和第一区域处的绝缘体通过第一掩模图案化以形成多个第一开口。 然后，在第一开口处形成第一硅化物。 介电层和第二区域处的绝缘体通过第二掩模图案化以形成多个第二开口。 然后，在第二开口处形成第二硅化物。

公开(公告)号：US20140374805A1

公开(公告)日：2014-12-25

申请号：US13921221

申请日：2013-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ching Wu ,  Chih-Sen Huang ,  Ching-Wen Hung

IPC: H01L21/311 ,  H01L23/00

CPC classification number: H01L21/311 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823842 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A manufacturing method for a semiconductor device first provides a substrate having at least a first transistor formed thereon. The first transistor includes a first conductivity type. The first transistor further includes a first metal gate and a protecting layer covering sidewalls of the first metal gate. A portion of the first metal gate is removed to form a first recess and followed by removing a portion of the protecting layer to form a second recess. Then, an etch stop layer is formed in the second recess.

Abstract translation: 半导体器件的制造方法首先提供至少形成有第一晶体管的衬底。 第一晶体管包括第一导电类型。 第一晶体管还包括第一金属栅极和覆盖第一金属栅极的侧壁的保护层。 去除第一金属栅极的一部分以形成第一凹槽，然后除去保护层的一部分以形成第二凹槽。 然后，在第二凹部中形成蚀刻停止层。

公开(公告)号：US20140361352A1

公开(公告)日：2014-12-11

申请号：US13912173

申请日：2013-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Shih-Fang Tzou

IPC: H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28079 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device is provided herein and includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, wherein a bottom surface of the patterned mask layer is leveled with a top surface of the first interlayer dielectric. A second interlayer dielectric is then formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.

Abstract translation: 本发明提供一种制造半导体器件的方法，包括以下步骤。 首先，在基板上形成第一层间电介质。 然后，在基板上形成栅电极，其中栅电极的周围被第一层间电介质包围。 之后，在栅电极上形成图案化掩模层，其中图案化掩模层的底表面与第一层间电介质的顶表面平齐。 然后形成第二层间电介质以覆盖图案化掩模层的顶表面和每个侧表面。 最后，在第一层间电介质和第二层间电介质中形成自对准接触结构。

公开(公告)号：US20140264481A1

公开(公告)日：2014-09-18

申请号：US13802917

申请日：2013-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L21/768 ,  H01L23/538

CPC classification number: H01L21/76841 ,  H01L21/76844 ,  H01L23/485 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.

Abstract translation: 提供包括第一电介质层，第二电介质层，阻挡层和第二插塞的插塞结构。 其中具有第一插头的第一电介质层位于衬底上，其中第一插头物理地接触衬底中的源极/漏极。 具有暴露第一插头的开口的第二电介质层位于第一电介质层上。 阻挡层保形地覆盖开口，其中阻挡层具有底部和侧壁部分，并且底部部分是单层，并且在侧壁部分是双层的同时物理地接触第一插塞。 第二个塞子填充开口和阻挡层。 此外，还提供了形成插头结构的工艺。

公开(公告)号：US08836129B1

公开(公告)日：2014-09-16

申请号：US13802917

申请日：2013-03-14

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L21/76841 ,  H01L21/76844 ,  H01L23/485 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.

Abstract translation: 提供包括第一电介质层，第二电介质层，阻挡层和第二插塞的插塞结构。 其中具有第一插头的第一电介质层位于衬底上，其中第一插头物理地接触衬底中的源极/漏极。 具有暴露第一插头的开口的第二电介质层位于第一电介质层上。 阻挡层共形地覆盖开口，其中阻挡层具有底部部分和侧壁部分，并且底部部分是单层，并且在侧壁部分是双层的同时物理地接触第一插塞。 第二个塞子填充开口和阻挡层。 此外，还提供了形成插头结构的工艺。

公开(公告)号：US20140162424A1

公开(公告)日：2014-06-12

申请号：US14182257

申请日：2014-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L29/66

CPC classification number: H01L29/66575 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/772 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a region; forming a gate structure on the region of the substrate; forming a raised epitaxial layer in the substrate adjacent to two sides of the gate structure; covering a dielectric layer on the gate structure and the raised epitaxial layer; and using a planarizing process to partially remove the dielectric layer and the gate structure such that the surface of the gate structure is even with the surface of the raised epitaxial layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有区域的衬底; 在所述基板的区域上形成栅极结构; 在所述衬底中邻近所述栅极结构的两侧形成凸起的外延层; 覆盖栅极结构和凸起的外延层上的介电层; 并且使用平坦化工艺来部分去除电介质层和栅极结构，使得栅极结构的表面与凸起的外延层的表面均匀。

公开(公告)号：US20140154852A1

公开(公告)日：2014-06-05

申请号：US13705183

申请日：2012-12-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Ching-Pin Hsu

IPC: H01L29/66

CPC classification number: H01L21/76816 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.

Abstract translation: 本发明提供一种形成具有金属连接的半导体结构的方法。 提供衬底，并在其上形成晶体管和第一ILD层。 第一接触插塞形成在第一ILD层中以电连接源极/漏极区域。 在第一ILD层上形成第二ILD层和第三ILD层。 形成在栅极上方的第一开口和在第一接触插塞上方的第二开口，其中第一接触插塞的深度比第二开口的深度深。 接下来，加深第一开口和第二开口。 最后，将金属层填充到第一开口和第二开口中，以分别形成第一金属连接和第二金属连接。

公开(公告)号：US12207564B2

公开(公告)日：2025-01-21

申请号：US18219713

申请日：2023-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yu-Ping Wang

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.