公开(公告)号：US20050160236A1

公开(公告)日：2005-07-21

申请号：US10761044

申请日：2004-01-20

Applicant: Gregory Tierney ,  Stephen Van Doren ,  Simon Steely

Inventor： Gregory Tierney ,  Stephen Van Doren ,  Simon Steely

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0813 ,  G06F12/0828 ,  G06F2212/2542

Abstract: A system comprises a first node including data having an associated D-state and a second node operative to provide a source broadcast requesting the data. The first node is operative in response to the source broadcast to provide the data to the second node and transition the state associated with the data at the first node from the D-state to an O-state without concurrently updating memory. An S-state is associated with the data at the second node.

Abstract translation: 系统包括包括具有相关D状态的数据的第一节点和用于提供请求数据的源广播的第二节点。 第一节点响应于源广播而操作以向第二节点提供数据，并将与第一节点处的数据相关联的状态从D状态转换到O状态，而不同时更新存储器。 S状态与第二节点处的数据相关联。

公开(公告)号：US06895476B2

公开(公告)日：2005-05-17

申请号：US10263743

申请日：2002-10-03

Applicant: Gregory E. Tierney ,  Stephen R. Van Doren

Inventor： Gregory E. Tierney ,  Stephen R. Van Doren

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0828

Abstract: A retry-based mechanism resolves late race conditions in a computer system between a first processor writing modified data back to main memory and a second processor trying to obtain a copy of the modified data. A low occupancy cache coherency protocol tracks ownership and sharing status of memory blocks. When a memory reference operation forwarded from the second processor results in a miss at the first processor's cache, because the requested memory block was written back to memory, the first processor issues a Retry command to the second processor. In response to the Retry command, the second processor issues another memory reference operation. This time, however, the operation explicitly specifies the version of the memory block being written back to main memory. Once the memory block has been written back to main memory, thereby providing main memory with the desired version, a copy is sent to the second processor.

Abstract translation: 基于重试的机制解决了在将修改后的数据写回到主存储器的第一处理器和试图获得修改的数据的副本的第二处理器之间的计算机系统中的后期竞争条件。 低占用高速缓存一致性协议跟踪内存块的所有权和共享状态。 当从第二处理器转发的存储器参考操作导致第一处理器的高速缓存中的未命中时，由于所请求的存储器块被写回存储器，所以第一处理器向第二处理器发出重试命令。 响应于重试命令，第二个处理器发出另一个内存引用操作。 但是，这一次，操作显然指定要写回主存储器的内存块的版本。 一旦存储器块被写回主存储器，从而为主存储器提供所需的版本，则将副本发送到第二处理器。

公开(公告)号：US20040268061A1

公开(公告)日：2004-12-30

申请号：US10896151

申请日：2004-07-20

Inventor： Manoj Khare ,  Lily P. Looi ,  Akhilesh Kumar

IPC: G06F012/00

CPC classification number: G06F12/0831 ,  G06F12/0804 ,  G06F12/0828

Abstract: A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.

公开(公告)号：US06829683B1

公开(公告)日：2004-12-07

申请号：US09910572

申请日：2001-07-20

Applicant: Jeffrey S. Kuskin

Inventor： Jeffrey S. Kuskin

IPC: G06F1200

CPC classification number: G06F12/0828 ,  G06F2212/2542

Abstract: A processor (300) in a distributed shared memory system (10) has ownership of a cache line. The processor modifies the cache line and wishes to update the home memory (17) of the cache line with the modification. The processor (300) generates a return request for routing by a processor interface (24). Meanwhile, a second processor (400) wishes to obtain ownership of the cache line and sends a read request to a memory directory (22) associated with the home memory (17) of the cache line. The memory directory (22) generates an intervention request towards the processor interface (24) corresponding to the last known location of the cache line. The processor interface (24) has now forwarded the return request to the memory directory (22) but subsequent to the read request from the second processor (400). Rather than waiting for an acknowledgment from the memory directory (22) that the return request has been processed, the processor interface (24) sends an intervention response to the second processor that includes the modified cache line.

Abstract translation: 分布式共享存储器系统（10）中的处理器（300）具有高速缓存行的所有权。 处理器修改高速缓存线并希望通过修改来更新高速缓存线的家用存储器（17）。 处理器（300）生成由处理器接口（24）进行路由的返回请求。 同时，第二处理器（400）希望获得高速缓存线的所有权，并将读请求发送到与高速缓存行的家用存储器（17）相关联的存储器目录（22）。 存储器目录（22）产生对应于高速缓存行的最后已知位置的处理器接口（24）的干预请求。 处理器接口（24）现在已经将返回请求转发到存储器目录（22），但是在来自第二处理器（400）的读取请求之后。 而不是等待从存储器目录（22）确认已经处理返回请求的确认，处理器接口（24）向包括修改的高速缓存行的第二处理器发送干预响应。

公开(公告)号：US06751720B2

公开(公告)日：2004-06-15

申请号：US10042054

申请日：2002-01-07

Applicant: Luiz André Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk ,  Robert J. Stets, Jr. ,  Mosur Kumaraswamy Ravishankar

Inventor： Luiz André Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk ,  Robert J. Stets, Jr. ,  Mosur Kumaraswamy Ravishankar

IPC: G06F1200

CPC classification number: G06F12/0826 ,  G06F12/0828 ,  G06F2212/621

Abstract: L1 cache synonyms in a two-level cache system are detected and resolved by logic in the L2 cache. Duplicate copies of the L1 cache tags and state (“Dtags”) are maintained in the L2 cache. After a miss occurs in the L1 cache, the Dtags in the second-level cache that correspond to all possible synonym locations in the L1 cache are searched for synonyms. If a synonym is found, the L2 cache notifies the L1 cache where the requested cache line can be found in the L1 cache. The L1 cache then copies the cache line from the location where the synonym was found to the location where the miss occurred, and it invalidates the cache line at the original location. The Dtags in the second-level cache are updated to reflect the changes made in the L1 cache.

Abstract translation: 二级缓存系统中的L1缓存同义词通过L2缓存中的逻辑进行检测和解析。 L1缓存标签和状态（“Dtags”）的重复副本被保留在L2高速缓存中。 在L1高速缓存中出现未命中之后，搜索对应于L1高速缓存中所有可能的同义词位置的二级高速缓存中的Dtags同义词。 如果发现同义词，则L2缓存通知L1缓存，其中可以在L1缓存中找到所请求的高速缓存行。 然后，L1高速缓存从发现同义词的位置复制缓存行到发生未命中的位置，并且使原始位置的高速缓存行无效。 更新二级缓存中的Dtags以反映L1缓存中所做的更改。

公开(公告)号：US20040068613A1

公开(公告)日：2004-04-08

申请号：US10263743

申请日：2002-10-03

Inventor： Gregory E. Tierney ,  Stephen R. Van Doren

IPC: G06F012/00

CPC classification number: G06F12/0828

Abstract: A retry-based mechanism resolves late race conditions in a computer system between a first processor writing modified data back to main memory and a second processor trying to obtain a copy of the modified data. A low occupancy cache coherency protocol tracks ownership and sharing status of memory blocks. When a memory reference operation forwarded from the second processor results in a miss at the first processor's cache, because the requested memory block was written back to memory, the first processor issues a Retry command to the second processor. In response to the Retry command, the second processor issues another memory reference operation. This time, however, the operation explicitly specifies the version of the memory block being written back to main memory. Once the memory block has been written back to main memory, thereby providing main memory with the desired version, a copy is sent to the second processor.

Abstract translation: 基于重试的机制解决了在将修改后的数据写回到主存储器的第一处理器和尝试获得修改的数据的副本的第二处理器之间的计算机系统中的后期竞争条件。 低占用高速缓存一致性协议跟踪内存块的所有权和共享状态。 当从第二处理器转发的存储器参考操作导致第一处理器的高速缓存中的未命中时，由于所请求的存储器块被写回存储器，所以第一处理器向第二处理器发出重试命令。 响应于重试命令，第二个处理器发出另一个内存引用操作。 但是，这一次，操作显然指定要写回主存储器的内存块的版本。 一旦存储器块被写回主存储器，从而为主存储器提供所需的版本，则将副本发送到第二处理器。

公开(公告)号：US20030023814A1

公开(公告)日：2003-01-30

申请号：US10042054

申请日：2002-01-07

Inventor： Luiz Andre Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk ,  Robert J. Stets JR. ,  Mosur Kumaraswamy Ravishankar

IPC: G06F012/00 ,  G06F012/10 ,  G06F012/16

CPC classification number: G06F12/0826 ,  G06F12/0828 ,  G06F2212/621

Abstract: L1 cache synonyms in a two-level cache system are detected and resolved by logic in the L2 cache. Duplicate copies of the L1 cache tags and state (nullDtagsnull) are maintained in the L2 cache. After a miss occurs in the L1 cache, the Dtags in the second-level cache that correspond to all possible synonym locations in the L1 cache are searched for synonyms. If a synonym is found, the L2 cache notifies the L1 cache where the requested cache line can be found in the L1 cache. The L1 cache then copies the cache line from the location where the synonym was found to the location where the miss occurred, and it invalidates the cache line at the original location. The Dtags in the second-level cache are updated to reflect the changes made in the L1 cache.

Abstract translation: 二级缓存系统中的L1缓存同义词通过L2缓存中的逻辑进行检测和解析。 L1缓存标签和状态（“Dtags”）的重复副本被保留在L2高速缓存中。 在L1高速缓存中出现未命中之后，搜索对应于L1高速缓存中所有可能的同义词位置的二级高速缓存中的Dtags同义词。 如果发现同义词，则L2缓存通知L1缓存，其中可以在L1缓存中找到所请求的高速缓存行。 然后，L1高速缓存从发现同义词的位置复制缓存行到发生未命中的位置，并且使原始位置的高速缓存行无效。 更新二级缓存中的Dtags以反映L1缓存中所做的更改。

公开(公告)号：US20020199066A1

公开(公告)日：2002-12-26

申请号：US10186118

申请日：2002-06-26

Inventor： Shailender Chaudhry ,  Marc Tremblay

IPC: G06F012/00 ,  G06F012/16

CPC classification number: G06F9/3834 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0828 ,  G06F12/0862 ,  Y10T74/1545

Abstract: One embodiment of the present invention provides a system that facilitates speculative load operations in a multiprocessor system. The system operates by maintaining a record of speculative load operations that have completed at a processor in the multiprocessor system, wherein a speculative load operation is a load operation that is speculatively initiated before a preceding load operation has returned. Next, the system receives an invalidation signal at an L1 cache that is coupled to the processor, wherein the invalidation signal indicates that a specific line in the L1 cache is to be invalidated. In response to this invalidation signal, the system examines the record of speculative load operations to determine if there exists a matching speculative load operation that is completed and is directed to the same location in the L1 cache that the invalidation signal is directed to. If there exists a matching speculative load operation, the system replays the matching speculative load operation so that the matching speculative load operation takes place after an event that caused the invalidation signal completes.

Abstract translation: 本发明的一个实施例提供了一种便于多处理器系统中的推测加载操作的系统。 该系统通过维持在多处理器系统中的处理器处已经完成的投机负载操作的记录来进行操作，其中推测加载操作是在先前加载操作返回之前被推测启动的加载操作。 接下来，系统在耦合到处理器的L1高速缓存处接收无效信号，其中无效信号指示L1高速缓存中的特定行将被无效。 响应于该无效信号，系统检查投机负载操作的记录，以确定是否存在完成的匹配的推测加载操作，并且被引导到无效信号所针对的L1高速缓存中的相同位置。 如果存在匹配的推测加载操作，则系统重播匹配的推测加载操作，使得匹配的推测加载操作在导致无效信号完成的事件之后发生。

公开(公告)号：US20020129208A1

公开(公告)日：2002-09-12

申请号：US10042008

申请日：2002-01-07

Applicant: Compaq Information Technologies, Group, L.P.

Inventor： Luiz A. Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk ,  Robert J. Stets ,  Mosur K. Ravishankar

IPC: G06F012/08

CPC classification number: G06F12/0826 ,  G06F12/0828 ,  G06F2212/621 ,  Y10S707/99938 ,  Y10S707/99952

Abstract: In a chip multiprocessor system, the coherence protocol is split into two cooperating protocols implemented by different hardware modules. One protocol is responsible for cache coherence management within the chip, and is implemented by a second-level cache controller. The other protocol is responsible for cache coherence management across chip multiprocessor nodes, and is implemented by separate cache coherence protocol engines. The cache controller and the protocol engine within each node communicate and synchronize memory transactions involving multiple nodes to maintain cache coherence within and across the nodes. The present invention addresses race conditions that arise during this communication and synchronization.

Abstract translation: 在芯片多处理器系统中，相干协议分为两个由不同硬件模块实现的协同协议。 一个协议负责芯片内的高速缓存一致性管理，并由二级缓存控制器实现。 另一个协议负责跨芯片多处理器节点的缓存一致性管理，并由单独的缓存一致性协议引擎实现。 每个节点内的高速缓存控制器和协议引擎通信和同步涉及多个节点的存储器事务，以保持节点内和跨节点的高速缓存一致性。 本发明解决了在该通信和同步期间出现的竞争条件。

公开(公告)号：US06415361B1

公开(公告)日：2002-07-02

申请号：US09487348

申请日：2000-01-19

Applicant: Sang Man Moh ,  Jong Seok Han ,  An Do Ki ,  Woo Jong Hahn ,  Suk Han Yoon ,  Gil Rok Oh

Inventor： Sang Man Moh ,  Jong Seok Han ,  An Do Ki ,  Woo Jong Hahn ,  Suk Han Yoon ,  Gil Rok Oh

IPC: G06F1200

CPC classification number: G06F12/0828 ,  G06F2212/2542

Abstract: An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.

Abstract translation: 一种用于控制位于节点总线和互连网络之间以执行高速缓存一致性协议的计算节点中的高速缓存的装置包括：用于与节点总线接口的节点总线接口; 用于与互连网络对接的互连网络接口; 用于控制高速缓存以执行高速缓存一致性协议的高速缓存控制逻辑装置; 耦合在所述节点总线接口和所述高速缓存控制逻辑装置之间的总线端双端口事务缓冲器，用于缓冲从计算节点中包含的本地处理器请求和应答的事务; 以及耦合在所述互连网络接口和所述高速缓存控制逻辑之间的网络侧双端口事务缓冲器，用于缓存从耦合到互连网络的另一个计算节点中包含的远程处理器请求和回复的事务。