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    Controlling access to groups of memory pages in a virtualized environment
    82.
    发明授权
    Controlling access to groups of memory pages in a virtualized environment 有权
    控制对虚拟化环境中的内存页组的访问

    公开(公告)号：US09098427B2

    公开(公告)日：2015-08-04

    申请号：US13716447

    申请日：2012-12-17

    Applicant: Intel Corporation

    Inventor： Baohong Liu ,  Ritu Sood ,  Kuo-Lang Tseng ,  Madhukar Tallam

    IPC: G06F12/00 ,  G06F12/10 ,  G06F12/14

    CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/145 ,  G06F2009/45583 ,  G06F2212/151 ,  G06F2212/657

    Abstract: Embodiments of an invention for controlling access to groups of memory pages in a virtualized environment are disclosed. In one embodiment, a processor includes a virtualization unit and a memory management unit. The virtualization unit is to transfer control of the processor to a virtual machine. The memory management unit is to perform, in response to an attempt to execute on the virtual machine an instruction stored on a first page, a page walk through a paging structure to find a second page and to allow access to the second page without exiting the virtual machine based at least in part on a bit being set in a leaf level entry corresponding to the second page in the paging structure and a corresponding bit being set in each entry corresponding to the first page in each level of the paging structure.

    Abstract translation: 公开了一种用于控制对虚拟化环境中的存储器页组的访问的发明的实施例。 在一个实施例中，处理器包括虚拟化单元和存储器管理单元。 虚拟化单元将处理器的控制转移到虚拟机。 存储器管理单元响应于尝试在虚拟机上执行存储在第一页面上的指令，执行通过寻呼结构寻找第二页面的页面，并且允许访问第二页面而不退出 虚拟机至少部分地基于在寻呼结构中对应于第二页的叶级别条目中设置一个位，并且在与寻呼结构的每个级别中的第一页对应的每个条目中设置相应的位。

    Power Reduction for Fully Associated Translation Lookaside Buffer
    83.
    发明申请
    Power Reduction for Fully Associated Translation Lookaside Buffer 有权
    完全相关的翻译后备缓冲区的功率降低

    公开(公告)号：US20150213153A1

    公开(公告)日：2015-07-30

    申请号：US14163096

    申请日：2014-01-24

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： Manish Shah ,  Gideon Levinsky

    IPC: G06F17/30 ,  G06F12/10 ,  G11C15/00

    CPC classification number: G06F17/30982 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2212/1028 ,  G06F2212/301 ,  G06F2212/684 ,  G11C15/00 ,  Y02D10/13

    Abstract: An apparatus and method for saving power during TLB searches is disclosed. In one embodiment, a TLB includes a CAM having a plurality of entries each storing a virtual address, and enable logic coupled to the CAM. Responsive to initiation of a TLB query by a thread executing on a processor that includes the TLB, the enable logic is configured to enable only those CAM entries that are associated with the initiating thread. Entries in the CAM not associated with the thread are not enabled. Accordingly, an initial search of the TLB for responsive to the query is conducted only in the CAM entries that are associated with the thread. Those CAM entries that are not associated with the thread are not searched. As a result, dynamic power consumption during TLB searches may be reduced.

    Abstract translation: 公开了一种在TLB搜索中节省电力的装置和方法。 在一个实施例中，TLB包括具有多个条目的CAM，每个条目存储虚拟地址，并且使能耦合到CAM的逻辑。 响应于在包括TLB的处理器上执行的线程启动TLB查询，启用逻辑被配置为仅启用与启动线程相关联的那些CAM条目。 未与线程相关联的CAM中的条目未启用。 因此，仅在与线程相关联的CAM条目中进行用于响应于查询的TLB的初始搜索。 不搜索与线程无关的那些CAM条目。 因此，TLB搜索中的动态功耗可能会降低。

    Source-target relations mapping
    84.
    发明授权
    Source-target relations mapping 有权
    源 - 目标关系映射

    公开(公告)号：US09086818B2

    公开(公告)日：2015-07-21

    申请号：US13774959

    申请日：2013-02-22

    Applicant: International Business Machines Corporation

    Inventor： Michael T. Benhase ,  Theresa M. Brown ,  Lokesh M. Gupta ,  Carol S. Mellgren

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0605 ,  G06F3/065 ,  G06F3/067 ,  G06F12/1036

    Abstract: A data preservation function is provided which, in one embodiment, includes indicating by a map, usage of a particular map extent range by a relationship between a source extent range of storage locations on a source storage device containing data to be preserved in the source extent range, and a target extent range mapped to the map particular extent range. In another aspect, in response to receipt of a data preservation command, a data preservation operation is performed including determining whether a map indicates availability of a map extent range mapped to the identified target extent range. Upon determining that a particular map indicates availability of a map extent range mapped to the identified target extent range, a relationship between the identified source extent range and the identified target extent range is established. Other features and aspects may be realized, depending upon the particular application.

    Abstract translation: 提供了一种数据保存功能，其在一个实施例中包括通过地图指示特定地图范围范围的使用，该源的范围在源存储设备上的源存储设备的源盘区范围之间的关系，该源存储设备包含要保留在源盘区中的数据 范围和映射到地图特定范围的目标范围范围。 在另一方面，响应于接收到数据保存命令，执行数据保存操作，包括确定映射是否指示映射到所识别的目标范围范围的映射范围范围的可用性。 在确定特定地图指示映射到所识别的目标范围范围的地图范围范围的可用性时，确定所识别的源范围范围和所识别的目标范围范围之间的关系。 可以根据具体应用实现其它特征和方面。

    DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION IN AN EMULATED ENVIRONMENT
    85.
    发明申请
    DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION IN AN EMULATED ENVIRONMENT 有权
    动态地址翻译与仿真环境中的保护

    公开(公告)号：US20150169437A1

    公开(公告)日：2015-06-18

    申请号：US14634020

    申请日：2015-02-27

    Applicant: International Business Machines Corporation

    Inventor： Dan F. GREINER ,  Charles W. GAINEY, JR. ,  Lisa C. HELLER ,  Damian L. OSISEK ,  Erwin PFEFFER ,  Timothy J. SLEGEL ,  Charles F. WEBB

    IPC: G06F12/02 ,  G06F12/10 ,  G06F12/14

    CPC classification number: G06F12/1027 ,  G06F9/30047 ,  G06F12/0215 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/145 ,  G06F2212/1052 ,  G06F2212/654 ,  G06F2212/656 ,  G06F2212/68

    Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled.

    Abstract translation: 提供的是增强的动态地址转换设施。 在一个实施例中，首先获得要被翻译的虚拟地址，并且获得翻译表层级的翻译表的初始起始地址。 基于获得的初始来源，获得段表条目。 段表项被配置为包含格式控制和访问有效性字段。 如果启用格式控制和访问有效性字段，则段表条目还包含访问控制字段，提取保护字段和段帧绝对地址。 仅当访问控制字段与程序状态字或被仿真的程序指令的操作数提供的程序访问键匹配时才允许存储操作。 如果与虚拟地址相关联的程序访问密钥等于段访问控制字段或者没有启用读取保护字段，则允许获取操作。

    METHOD IN A MEMORY MANAGEMENT UNIT FOR MANAGING ADDRESS TRANSLATIONS IN TWO STAGES
    87.
    发明申请
    METHOD IN A MEMORY MANAGEMENT UNIT FOR MANAGING ADDRESS TRANSLATIONS IN TWO STAGES 有权
    用于在两个阶段管理地址转换的存储器管理单元中的方法

    公开(公告)号：US20150143072A1

    公开(公告)日：2015-05-21

    申请号：US14526686

    申请日：2014-10-29

    Applicant: STMicroelectronics International N.V.

    Inventor： Herve Sibert ,  Loic Pallardy

    IPC: G06F12/10

    CPC classification number: G06F12/1036 ,  G06F12/1009 ,  G06F2212/657

    Abstract: A memory management unit (MMU) may manage address translations. The MMU may obtain a first intermediate physical address (IPA) based on a first virtual address (VA) relating to a first memory access request. The MMU may identify, based on the first IPA, a first memory page entry in a second address translation table. The MMU may store, in a second cache memory, a first IPA-to-PA translation based on the identified first memory page entry. The MMU may store, in the second cache memory and in response to the identification of the first memory page entry, one or more additional IPA-to-PA translations that are based on corresponding one or more additional memory page entries in the second address translation table. The one or more additional memory page entries may be contiguous to the first memory page entry.

    Abstract translation: 内存管理单元（MMU）可以管理地址转换。 MMU可以基于与第一存储器访问请求相关的第一虚拟地址（VA）获得第一中间物理地址（IPA）。 MMU可以基于第一IPA识别第二地址转换表中的第一存储器页条目。 MMU可以在第二高速缓冲存储器中存储基于所识别的第一存储器页条目的第一IPA到PA转换。 MMU可以在第二高速缓冲存储器中存储并且响应于第一存储器页条目的标识，基于第二地址转换中的对应的一个或多个附加存储器页条目的一个或多个附加的IPA到PA转换 表。 一个或多个附加存储器页条目可以与第一存储器页条目相邻。

    HARDWARE VIRTUALIZATION FOR MEDIA PROCESSING
    88.
    发明申请
    HARDWARE VIRTUALIZATION FOR MEDIA PROCESSING 审中-公开
    用于媒体处理的硬件虚拟化

    公开(公告)号：US20150074310A1

    公开(公告)日：2015-03-12

    申请号：US14543007

    申请日：2014-11-17

    Applicant: Marvell World Trade Ltd.

    Inventor： Timor KARDASHOV ,  Maxim Kovalenko ,  Arie Elias ,  Guy Ray

    IPC: G06F13/26 ,  G06F9/48

    CPC classification number: G06F9/48 ,  G06F9/455 ,  G06F9/461 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5027 ,  G06F9/5077 ,  G06F12/1036 ,  G06F12/109 ,  G06F13/26

    Abstract: Methods and systems for implementing virtual processors are disclosed. For example, in an embodiment a processing apparatus configured to act as a plurality of virtual processors includes a first virtual program space that includes a first program execution memory, the first program execution memory including code to run a non-real-time operating system capable of supporting a one or more non-real-time applications, a second virtual program space that includes a second program execution memory, the second program execution memory including code to run one or more real-time processes, and a central processing unit (CPU) configured to operate in a first operating mode and a second operating mode, the CPU being configured to perform operating system and application activities using the first virtual program space for the first operating mode without using the second virtual program space and without appreciably interfering with the one or more real-time processes that are running in the second operating mode.

    Abstract translation: 公开了用于实现虚拟处理器的方法和系统。 例如，在实施例中，配置为充当多个虚拟处理器的处理装置包括包括第一程序执行存储器的第一虚拟程序空间，所述第一程序执行存储器包括运行非实时操作系统的代码 支持一个或多个非实时应用的第二虚拟程序空间，包括第二程序执行存储器的第二虚拟程序空间，所述第二程序执行存储器包括运行一个或多个实时进程的代码，以及中央处理单元（CPU ），其被配置为在第一操作模式和第二操作模式下操作，所述CPU被配置为使用所述第一操作模式的所述第一虚拟程序空间来执行操作系统和应用活动，而不使用所述第二虚拟程序空间，并且不明显地干扰 在第二操作模式下运行的一个或多个实时进程。

    Power Logic For Memory Address Conversion
    90.
    发明申请
    Power Logic For Memory Address Conversion 有权
    用于存储器地址转换的功率逻辑

    公开(公告)号：US20140380018A1

    公开(公告)日：2014-12-25

    申请号：US13926564

    申请日：2013-06-25

    Applicant: James E. Phillips ,  Wing Shek Wong ,  Charles Vitu

    Inventor： James E. Phillips ,  Wing Shek Wong ,  Charles Vitu

    IPC: G06F12/10

    CPC classification number: G06F12/1036 ,  G06F9/3001 ,  G06F9/32

    Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes conversion power logic to receive an instruction including an untranslated memory address, determine whether a code segment (CS) base address is equal to zero, and in response to a determination that the CS base address is equal to zero, execute the instruction using the untranslated memory address. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括多个核。 每个核心包括用于接收包括非翻译存储器地址的指令的转换功率逻辑，确定代码段（CS）基地址是否等于零，并且响应于CS基地址等于零的确定，执行指令 使用非翻译的内存地址。 描述和要求保护其他实施例。

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