公开(公告)号：US20180122431A1

公开(公告)日：2018-05-03

申请号：US15855609

申请日：2017-12-27

Applicant: lntel Corporation

Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

IPC: G11C7/10 ,  G06F9/30

CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

公开(公告)号：US20180122429A1

公开(公告)日：2018-05-03

申请号：US15855585

申请日：2017-12-27

Applicant: lntel Corporation

Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

IPC: G11C7/10 ,  G06F9/30

CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

公开(公告)号：US09921772B2

公开(公告)日：2018-03-20

申请号：US15253757

申请日：2016-08-31

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tsuyoshi Atsumi ,  Yasuhiko Kurosawa

IPC: G11C7/10 ,  G06F3/06 ,  G06F7/58 ,  G11C16/10 ,  G11C16/34

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0679 ,  G06F7/58 ,  G11C7/1006 ,  G11C7/1036 ,  G11C16/10 ,  G11C16/349

Abstract: A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2n−1 bytes, n being a number of registers included in the linear feedback shift register circuit.

公开(公告)号：US09846565B2

公开(公告)日：2017-12-19

申请号：US14349352

申请日：2011-10-27

Applicant: Matthew D. Pickett ,  R. Stanley Williams ,  Gilberto M. Ribeiro

Inventor： Matthew D. Pickett ,  R. Stanley Williams ,  Gilberto M. Ribeiro

IPC: G06F5/08 ,  G11C19/00 ,  G11C19/28 ,  G11C21/00 ,  G11C7/10

CPC classification number: G06F5/08 ,  G11C7/1012 ,  G11C7/1036 ,  G11C19/00 ,  G11C19/28 ,  G11C21/00

Abstract: Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability. The memory includes a plurality of ring registers to store data words. A contiguous subset of data words is shiftable between sets of the ring registers of the plurality from a first location to a second location within the memory. The contiguous subset of data words has a size that is smaller than a total size of the memory. The memory shifts only data words stored inside the contiguous subset when the contiguous subset is shifted.

公开(公告)号：US20170316751A1

公开(公告)日：2017-11-02

申请号：US15518389

申请日：2016-09-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.

Inventor： Zheng WANG

IPC: G09G3/36 ,  G11C7/10 ,  G11C19/28 ,  G11C29/00 ,  G11C19/30

CPC classification number: G09G3/3685 ,  G09G3/3677 ,  G09G2310/0283 ,  G09G2310/0286 ,  G11C7/1036 ,  G11C19/18 ,  G11C19/184 ,  G11C19/28 ,  G11C19/287 ,  G11C19/30 ,  G11C29/022 ,  G11C29/86

Abstract: A shift register unit, a gate line driving device includes multiple stages of the shift register units, and a driving method for being applied to the shift register unit; the shift register unit includes: an input module connected between an input terminal and a pull-up node, and configured to charge the pull-up node; an output module connected between the pull-up node, a first clock signal terminal and an output terminal, and configured to output to the output terminal a first clock signal received at the first clock signal terminal; a pull-up node reset module connected between a reset terminal, a pull-down node and the pull-up node, and configured to reset the pull-up node; and an output reset module connected between a second clock signal terminal, the pull-down node and the output terminal, and configured to reset the output terminal.

公开(公告)号：US20170269865A1

公开(公告)日：2017-09-21

申请号：US15072147

申请日：2016-03-16

Applicant: Micron Technology, Inc.

Inventor： Jeremiah J. Willcock ,  Perry V. Lea ,  Anton Korzh

IPC: G06F3/06 ,  G06T1/00 ,  H04N19/186 ,  G11C11/4091

CPC classification number: G06F3/0638 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0673 ,  G06T1/0007 ,  G06T1/60 ,  G11C7/1006 ,  G11C7/1036 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/005 ,  G11C2207/102 ,  G11C2207/104 ,  H04N19/186

Abstract: The present disclosure includes apparatuses and methods for operations using compressed and decompressed data. An example method includes receiving compressed data to a processing in memory (PIM) device and decompressing the compressed data on the PIM device.

公开(公告)号：US09740636B2

公开(公告)日：2017-08-22

申请号：US15064066

申请日：2016-03-08

Applicant: Renesas Electronics Corporation

Inventor： Masayuki Ito ,  Hideki Sugimoto

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/14 ,  G11C7/10 ,  G06F9/455 ,  G06F13/16

CPC classification number: G06F12/14 ,  G06F9/45558 ,  G06F13/1663 ,  G06F13/1694 ,  G06F13/385 ,  G06F2009/45583 ,  G06F2212/1052 ,  G11C7/1036 ,  Y02D10/14 ,  Y02D10/151

Abstract: According to an embodiment, an information processing apparatus includes a plurality of cores, a shared resource that can be shared by the plurality of cores, and local registers that store configuration information peculiar to the respective cores. The shared resource is provided independently from the plurality of cores. The local registers are provided to the respective cores. This makes it possible to provide an information processing apparatus that can suppress increase in hardware resources even when the number of cores composing a multi-core system increases.

公开(公告)号：US20170160939A1

公开(公告)日：2017-06-08

申请号：US15253757

申请日：2016-08-31

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tsuyoshi ATSUMI ,  Yasuhiko KUROSAWA

IPC: G06F3/06 ,  G06F7/58

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0679 ,  G06F7/58 ,  G11C7/1006 ,  G11C7/1036 ,  G11C16/10 ,  G11C16/349

Abstract: A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2n−1 bytes, n being a number of registers included in the linear feedback shift register circuit.

公开(公告)号：US09672143B2

公开(公告)日：2017-06-06

申请号：US14950017

申请日：2015-11-24

Applicant: III HOLDINGS 2, LLC

Inventor： Prashant R. Chandra ,  Thomas A. Volpe ,  Mark Bradley Davis ,  Niall Joseph Dalton

IPC: G06F12/00 ,  G06F9/54 ,  G06F13/16 ,  G11C7/10 ,  G11C21/00 ,  G06F13/00 ,  G06F13/28 ,  G06F15/173 ,  G06F12/02

CPC classification number: G06F12/00 ,  G06F9/54 ,  G06F12/0223 ,  G06F13/1663 ,  G06F15/17331 ,  G06F15/17375 ,  G11C7/1036 ,  G11C7/1072 ,  G11C21/00 ,  Y02D10/14

Abstract: A data processing node has an inter-node messaging module including a plurality of sets of registers each defining an instance of a GET/PUT context and a plurality of data processing cores each coupled to the inter-node messaging module. Each one of the data processing cores includes a mapping function for mapping each one of a plurality of user level processes to a different one of the sets of registers and thereby to a respective GET/PUT context instance. Mapping each one of the user level processes to the different one of the sets of registers enables a particular one of the user level processes to utilize the respective GET/PUT context instance thereof for performing a GET/PUT action to a ring buffer of a different data processing node coupled to the data processing node through a fabric without involvement of an operating system of any one of the data processing cores.

公开(公告)号：US09666251B2

公开(公告)日：2017-05-30

申请号：US14744655

申请日：2015-06-19

Applicant: Texas Instruments Incorporated

Inventor： Gopalkrishna Ullal Nayak ,  Matthew Craig Bullock

IPC: H01L21/66 ,  G11C7/10 ,  G11C29/04

CPC classification number: G11C7/1051 ,  G11C7/1036 ,  G11C29/04 ,  H01L22/14 ,  H01L22/20

Abstract: In a semiconductor chip for an electronic device, a programmable trim code is independent from a default trim code. An output trim code is produced by selecting either the default trim code or the programmable trim code. The default trim code for a plurality of the semiconductor chips is set by forming metal interconnects according to a first metal layout in a metal interconnect layer during fabrication of at least one of the semiconductor chips. The default trim code is reset by forming the metal interconnects according to a second metal layout in the metal interconnect layer during fabrication of subsequent semiconductor chips.