公开(公告)号：US09928920B2

公开(公告)日：2018-03-27

申请号：US14976842

申请日：2015-12-21

Applicant: Toshiba Memory Corporation

Inventor： Yasuhiko Kurosawa ,  Tsuyoshi Atsumi ,  Masanobu Shirakawa ,  Tokumasa Hara ,  Naoya Tokiwa

IPC: G11C16/34 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C16/26 ,  G11C7/04 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/3404 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C29/52

Abstract: According to one embodiment, a temperature of a non-volatile memory or an ambient temperature of the non-volatile memory is acquired. A distribution of a threshold voltage, which is corrected according to the acquired temperature, is acquired from the non-volatile memory. Read voltages related to the reading of data are detected from the distribution. Error correction is performed for data read from the non-volatile memory, using the read voltages. The detected read voltages are separately corrected on the basis of the acquired temperature when the error correction has failed.

公开(公告)号：US10884706B2

公开(公告)日：2021-01-05

申请号：US16567898

申请日：2019-09-11

Applicant: Toshiba Memory Corporation

Inventor： Tsuyoshi Atsumi ,  Yasuhiko Kurosawa ,  Yohei Koganei ,  Yuji Nagai

IPC: G06F7/58 ,  H04L9/06

Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.

公开(公告)号：US10014059B2

公开(公告)日：2018-07-03

申请号：US15686833

申请日：2017-08-25

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tsuyoshi Atsumi

IPC: G11C11/34 ,  G11C16/26 ,  G11C29/02 ,  G11C16/34 ,  G11C29/04

CPC classification number: G11C16/26 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: According to one embodiment, a distribution of threshold voltages of a plurality of memory cells is acquired from a nonvolatile memory which includes the plurality of memory cells, a malfunction state occurring in the nonvolatile memory is identified based on a shape of the distribution, and a read voltage when data is read out of the nonvolatile memory is set to a voltage value corresponding to a type of the malfunction state.

公开(公告)号：US10459691B2

公开(公告)日：2019-10-29

申请号：US15448558

申请日：2017-03-02

Applicant: Toshiba Memory Corporation

Inventor： Tsuyoshi Atsumi ,  Yasuhiko Kurosawa ,  Yohei Koganei ,  Yuji Nagai

IPC: G06F7/58 ,  H04L9/06

Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.

公开(公告)号：US09921772B2

公开(公告)日：2018-03-20

申请号：US15253757

申请日：2016-08-31

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tsuyoshi Atsumi ,  Yasuhiko Kurosawa

IPC: G11C7/10 ,  G06F3/06 ,  G06F7/58 ,  G11C16/10 ,  G11C16/34

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0679 ,  G06F7/58 ,  G11C7/1006 ,  G11C7/1036 ,  G11C16/10 ,  G11C16/349

Abstract: A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2n−1 bytes, n being a number of registers included in the linear feedback shift register circuit.

公开(公告)号：US09773563B2

公开(公告)日：2017-09-26

申请号：US14755900

申请日：2015-06-30

Applicant: Toshiba Memory Corporation

Inventor： Tsuyoshi Atsumi

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/34 ,  G11C29/02 ,  G11C29/04

CPC classification number: G11C16/26 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: According to one embodiment, a distribution of threshold voltages of a plurality of memory cells is acquired from a nonvolatile memory which includes the plurality of memory cells, a malfunction state occurring in the nonvolatile memory is identified based on a shape of the distribution, and a read voltage when data is read out of the nonvolatile memory is set to a voltage value corresponding to a type of the malfunction state.

公开(公告)号：US10430101B2

公开(公告)日：2019-10-01

申请号：US15925617

申请日：2018-03-19

Applicant: Toshiba Memory Corporation

Inventor： Tsuyoshi Atsumi ,  Yasuhiko Kurosawa

IPC: G11C7/10 ,  G06F3/06 ,  G06F7/58 ,  G11C16/10 ,  G11C16/34

Abstract: A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2n-1 bytes, n being a number of registers included in the linear feedback shift register circuit.