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    Fibre channel frame batching for IP transmission
    1.
    发明授权
    Fibre channel frame batching for IP transmission 有权
    光纤通道帧批量IP传输

    公开(公告)号：US07308001B2

    公开(公告)日：2007-12-11

    申请号：US10295359

    申请日：2002-11-15

    Applicant: William Collette ,  Bret Ketchum ,  Richard Kelley ,  Robert Engebretson ,  Mark Moran ,  Mike Morandi

    Inventor： William Collette ,  Bret Ketchum ,  Richard Kelley ,  Robert Engebretson ,  Mark Moran ,  Mike Morandi

    IPC: H04J3/16

    CPC classification number: H04L12/4633

    Abstract: A storage router and related method are presented for combining multiple Fibre Channel frames together into a single IP datagram for tunneling transmission over an Internet protocol network. The storage router operates by storing incoming Fibre Channel frames in a Fibre Channel frame buffer. When there is sufficient data in the buffer, multiple Fibre Channel frames are taken from the buffer and combined into a single IP datagram. The number of Fibre Channel frames to be combined can be established through a variety of tests, including total bytes of data, number of frames, or through a time-out mechanism. The network layer then fragments the datagram into data link level frames, such as 1500 byte Ethernet frames. When the IP datagram arrives at the final destination, the segmented IP datagram is reconstructed, and the multiple Fibre Channel frames are extracted from the IP datagram and passed on to the recipient Fibre Channel network.

    Abstract translation: 提出了存储路由器和相关方法，用于将多个光纤通道帧组合在一起成为用于通过因特网协议网络进行隧道传输的单个IP数据报。 存储路由器通过将进入的光纤通道帧存储在光纤通道帧缓冲​​器中来操作。 当缓冲器中有足够的数据时，从缓冲器中取出多个光纤通道帧，并将其组合成单个IP数据报。 要组合的光纤通道帧的数量可以通过各种测试来建立，包括数据的总字节数，帧数，或通过超时机制。 网络层然后将数据报分段成数据链路级帧，例如1500字节以太网帧。 当IP数据报到达最终目的地时，重建分段IP数据报，并从IP数据报提取多个光纤通道帧，并将其传递到接收光纤通道网络。

    Fiber channel architecture
    2.
    发明授权
    Fiber channel architecture 有权
    光纤通道架构

    公开(公告)号：US06981078B2

    公开(公告)日：2005-12-27

    申请号：US09922591

    申请日：2001-08-03

    Applicant: Harry V. Paul

    Inventor： Harry V. Paul

    IPC: G06F11/00 ,  G06F11/20 ,  G06F13/00 ,  G06F13/40 ,  H04L1/22 ,  H04L12/00 ,  H04L12/44 ,  H04L12/56

    CPC classification number: H04L49/557 ,  G06F11/2007 ,  H04L49/357

    Abstract: A fiber channel backplane configuration is capable of modular expansion, e.g., from 64 ports to 128 ports or 256 ports by a simple operation. The backplane includes connectors that provide permanent and jumper/vertical connections to support 64 user port switch in a single chassis. For a 128 port switch, two 64 port chassis are used. In the 128 port configuration, the connectors are configured to provide permanent and jumper/vertical connections to make intra-chassis and inter-chassis connections between the fabric switch and fabric input/output boards. Using jumper plugs, the jumper connectors provide vertical connections between the fiber input/output boards and fiber switch boards of two chassis. For a 256 port switch configuration, four 64 port chassis assemblies are used. The connectors are configured to provide each switch with permanent, vertical, horizontal, and diagonal connections to the fiber input/output boards of each of the four chassis.

    Abstract translation: 光纤通道背板配置能够通过简单的操作来模块化扩展，例如从64端口到128端口或256端口。 背板包括提供永久和跳线/垂直连接的连接器，以在单个机箱中支持64个用户端口交换机。 对于128端口交换机，使用两个64端口机箱。 在128端口配置中，连接器被配置为提供永久和跨接/垂直连接，以便在布架交换机和结构输入/输出板之间进行机箱内和机架间连接。 使用跳线插头，跳线连接器可在两个机箱的光纤输入/输出板和光纤交换板之间提供垂直连接。 对于256端口交换机配置，使用四个64端口机箱组件。 连接器被配置成为每个开关提供永久的，垂直的，水平的和对角线连接到四个机箱中的每一个的光纤输入/输出板。

    Deferred queuing in a buffered switch
    3.
    发明授权
    Deferred queuing in a buffered switch 有权
    在缓冲交换机中延迟排队

    公开(公告)号：US07260104B2

    公开(公告)日：2007-08-21

    申请号：US10020968

    申请日：2001-12-19

    Applicant: Steven G. Schmidt

    Inventor： Steven G. Schmidt

    IPC: H04L12/56

    CPC classification number: H04L49/3009 ,  H04L49/30 ,  H04L2012/5683

    Abstract: A method and apparatus for temporarily deferring transmission of packets/frames to a destination port in a buffered switch is disclosed. When a request for transmission of at least one packet/frame to the destination port is received, it is determined whether the destination port is available to receive the at least one packet/frame. The transmission of the at least one packet/frame is deferred when the destination port is not available to receive the at least one packet/frame. The packet/frame identifier and memory location for each deferred packet/frame is stored in a deferred queue and the process then repeats for the next packet/frame. Periodically, the apparatus attempts to transmit the packets/frames in the deferred queue to their respective destination ports.

    Abstract translation: 公开了一种用于暂时将缓存的交换机中的分组/帧传输到目的地端口的方法和装置。 当接收到至少一个分组/帧到目的地端口的传输请求时，确定目的端口是否可用于接收至少一个分组/帧。 当目的地端口不可用于接收至少一个分组/帧时，延迟至少一个分组/帧的传输。 每个延迟分组/帧的分组/帧标识符和存储器位置被存储在延迟队列中，然后该过程重复下一个分组/帧。 周期性地，设备尝试将延迟队列中的分组/帧传送到它们各自的目的端口。

    Method and apparatus for booting a microprocessor
    5.
    发明授权
    Method and apparatus for booting a microprocessor 有权
    用于引导微处理器的方法和装置

    公开(公告)号：US07032106B2

    公开(公告)日：2006-04-18

    申请号：US10026707

    申请日：2001-12-27

    Applicant: Joseph Horanzy ,  Akshay Mathur

    Inventor： Joseph Horanzy ,  Akshay Mathur

    IPC: G06F9/445 ,  G06F9/24

    CPC classification number: G06F15/177 ,  G06F9/4403 ,  G06F9/4405

    Abstract: A method and system for bootstrapping a processor from a volatile memory device connected to the processor is disclosed. The first processor is bootstrapped from flash device. The reset lines of the second processor are asserted. The boot code for the second processor is loaded from the flash device into the volatile memory device. The reset lines of the second processor are de-asserted, wherein the processor then boots from the boot code stored in the volatile memory device. The same boot-strapping method can be extended to multi-drop systems where number of secondary processor can be more than one. A switchable means for the second processor to boot from volatile memory as described or from flash memory. A method also describes a mechanism to boot from synchronous volatile memory devices.

    Abstract translation: 公开了一种用于从连接到处理器的易失性存储器件引导处理器的方法和系统。 第一个处理器从闪存设备引导。 第二处理器的复位线被断言。 用于第二处理器的引导代码从闪存设备加载到易失性存储器设备中。 第二处理器的复位线被取消断言，其中处理器然后从存储在易失性存储器件中的引导代码引导。 相同的启动方法可以扩展到多处理系统，其中二级处理器的数量可以多于一个。 用于第二处理器从易失性存储器引导的可切换装置，如从闪存中所述。 一种方法还描述了从同步易失性存储器设备引导的机制。

    Frame-level fibre channel CRC on switching platform
    7.
    发明授权
    Frame-level fibre channel CRC on switching platform 失效
    交换平台上的帧级光纤通道CRC

    公开(公告)号：US07391723B2

    公开(公告)日：2008-06-24

    申请号：US10420953

    申请日：2003-04-22

    Applicant: William C. Collette ,  Steve Flattum ,  Mark J. Vogel ,  Bret Ketchum

    Inventor： William C. Collette ,  Steve Flattum ,  Mark J. Vogel ,  Bret Ketchum

    IPC: H04J3/14 ,  H04B10/08 ,  H04L9/00 ,  H04L12/26 ,  H04L12/54 ,  H04M13/00

    CPC classification number: H04L12/56

    Abstract: A method and apparatus is presented for performing a sequence-level CRC calculation on fiber channel communications within a switching platform domain. A CRC generator searches the data communication for frames that contain the type of data for which a sequence-level CRC is desired, such as for a sequence containing SCSI data. If found, and the type of data allows multiple frames per sequence, the present invention creates a CRC value for the sequence. An intermediate CRC value is stored in a queue to allow the simultaneous calculation of sequence level CRC values for multiple frames. With inbound data, the sequence-level CRC is appended to the end of the sequence data. With outbound data, the calculated value is compared with the appended, expected value, With single-frame fiber channel protocols, the frame-level CRC value is obtained directly from the frames entering the switching platform domain. This value is placed in a local queue, from which it is appended to the data payload by a processor for transmission within the switching platform. When the single frame is leaving the switching platform domain, the flow of data leaving the switching platform domain is monitored and the frame-level CRC value calculated by the fiber channel controller is replaced with the original frame-level CRC value.

    Abstract translation: 提出了一种用于对交换平台域内的光纤通道通信进行序列级CRC计算的方法和装置。 CRC发生器在数据通信中搜索包含期望序列级CRC的数据类型的帧，例如包含SCSI数据的序列。 如果发现，并且数据类型允许每个序列多个帧，则本发明创建该序列的CRC值。 中间CRC值存储在队列中，以允许同时计算多个帧的序列级CRC值。 对于入站数据，序列级CRC附加到序列数据的末尾。 使用出站数据，将计算值与附加的预期值进行比较。对于单帧光纤通道协议，帧级CRC值直接从进入交换平台域的帧获得。 该值被放置在本地队列中，由处理器将其附加到数据有效负载以在交换平台内进行传输。 当单个帧离开交换平台域时，监视离开交换平台域的数据流，由光纤通道控制器计算的帧级CRC值被替换为原始帧级CRC值。

    Transmitter and receiver circuit
    9.
    发明授权
    Transmitter and receiver circuit 失效
    发射机和接收机电路

    公开(公告)号：US4736385A

    公开(公告)日：1988-04-05

    申请号：US7950

    申请日：1987-01-27

    Applicant: Warren R. Pratt ,  Charles R. Rogers ,  Dennis G. Cope

    Inventor： Warren R. Pratt ,  Charles R. Rogers ,  Dennis G. Cope

    IPC: H04L12/40 ,  H04L25/08 ,  H04B3/50

    CPC classification number: H04L12/40169 ,  H04L25/08

    Abstract: High frequency transmitter and receiver circuits are AC coupled for party line transmission over coaxial cable where the circuits are connectable to the cable by use of stinger taps and thereby eliminate the need to interrupt service when connecting the circuits to the cable. The transmitter circuit includes oppositely polled current sources which are alternately switched to the coaxial cable via the stinger tap or to a dummy load by current switches connected to data inputs via buffer circuits. A transmit enable circuit controls the current sources to be active or inactive and to prevent unbalances from saturating either current sources. The receiver includes a high input impedance biasing network and buffer amplifier that maintain the high input impedance even when power is off. Capacitance at the tap is reduced by a capacitor drive circuit which feeds input signal back to transmitter blocking diodes and to the trunk tap. A feed ahead network, differentiating network, and another buffer amplifier form a network for recovering the transmitted signal shape regardless of distance from the transmitter. A gated amplifier restores the shaped signal to logic levels ready for conversion to non-return-to-zero data. Filter and buffer circuits restrict level detection to signals in the frequency band of the transmitter. A threshold circuit sets the carrier sense detection level and a high gain amplifier converts signals above the threshold to ECL logic levels. After conversion of the ECL logic levels to TTL logic signals, a single shot produces a DC level from the logic level carrier signal. That DC carrier sense output enables data conversion circuits and drives a gate circuit for gating the gated amplifier.

    Abstract translation: 高频发射机和接收机电路通过同轴电缆进行交流耦合，通过使用支架分接头可以连接电缆，从而无需在将电路连接到电缆时中断服务。 发射机电路包括相对轮询的电流源，它们经由托管抽头交替地切换到同轴电缆，或者通过经由缓冲电路连接到数据输入端的电流开关进行虚拟负载。 发射使能电路控制电流源处于活动状态或不活动状态，并防止不均衡使电流源饱和。 接收器包括高输入阻抗偏置网络和缓冲放大器，即使在断电时也保持高输入阻抗。 水龙头的电容通过电容器驱动电路减少，该电路将输入信号反馈给发射器阻塞二极管和中继抽头。 前馈网络，差分网络和另一缓冲放大器形成用于恢复发射信号形状的网络，而与距离发射机的距离无关。 门控放大器将成形信号恢复到准备好转换为非归零数据的逻辑电平。 滤波器和缓冲电路将电平检测限制在发射机的频带中的信号。 阈值电路设置载波检测电平，高增益放大器将阈值以上的信号转换为ECL逻辑电平。 在ECL逻辑电平转换为TTL逻辑信号之后，单次触发从逻辑电平载波信号产生一个直流电平。 该直流载波检测输出使数据转换电路能够驱动门控电路门控门控放大器。

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