公开(公告)号：US06366443B1

公开(公告)日：2002-04-02

申请号：US08987463

申请日：1997-12-09

Applicant: Daniel Devoe ,  Alan D. Devoe ,  Lambert Devoe

Inventor： Daniel Devoe ,  Alan D. Devoe ,  Lambert Devoe

IPC: H01G406

CPC classification number: H01G4/232 ,  H01G4/228 ,  H05K1/0306 ,  H05K1/162

Abstract: A ceramic capacitor typically 10 mils to 340 mils square by typically 4-20 mils thickness with areas of metallization, or pads, to which electrical connections may be made on, typically, each of two opposite exterior surfaces, has embedded at least one, and normally two or more, metallization planes at close, typically 0.5 mil, separation. Each interior metallization plane connects through multiple redundant vias, as are preferably made by (ii) punching, (ii) drilling, (iii) laser drilling, or (iv) radiation patterning of a green ceramic sheet having a photosensitive binder, to an associated surface pad or trace. The vias are both numerous and redundant, typically being of 2 mil diameter on 10 mil centers in a pin grid array pattern over and through entire ceramic layers of the capacitor, permitting both (i) easy fabrication without exacting alignment or registration between layers, and (ii) low Equivalent Series Resistance (ESR) in the finished capacitor. The composite structure so created exhibits increased capacitance over that which would alternatively exist should no electrically-connected interior metallization planes be present.

Abstract translation: 陶瓷电容器通常为10密耳至340密耳平方，通常为4-20密耳厚度，具有金属化或焊盘的区域，电连接可以通常形成在两个相对的外表面上，每个都具有至少一个和 通常为两个或更多个金属化平面，接近，通常为0.5密耳，分离。 每个内部金属化平面通过多个冗余通孔连接，优选通过以下方式制成：（i）冲孔，（ii）钻孔，（iii）激光钻孔，或（iv）具有感光性粘合剂的生坯陶瓷片的辐射图案化， 表面垫或痕迹。 通孔是众多的和冗余的，通常在10密耳中心上的2密耳直径，在电容器的整个陶瓷层上方并且穿过电容器的整个陶瓷层，允许（i）易于制造而不精确对准或层之间的配准，以及 （ii）成品电容器中的低等效串联电阻（ESR）。 如此制造的复合结构表现出增加的电容，如果不存在电连接的内部金属化平面，则可能存在电容。 ...不再需要最大限度地实现最佳电容，外部焊盘尺寸适中，位置优越，优选从电容器的边缘取出，以防止环氧树脂粘合剂的芯吸，从而允许四舍五入 电容器的边缘为了抑制切屑。 尽管如此，尺寸较小的焊盘仍然比通过冗余地电连接到每个焊盘的多个通孔大得多，并且通常通过阴燃而容易可靠地电连接。

公开(公告)号：US06917509B1

公开(公告)日：2005-07-12

申请号：US10301335

申请日：2002-11-21

Applicant: Daniel F. Devoe ,  Lambert Devoe ,  Alan D. Devoe

Inventor： Daniel F. Devoe ,  Lambert Devoe ,  Alan D. Devoe

IPC: H01G2/06 ,  H01G4/228 ,  H05K3/32 ,  H05K3/34 ,  H01G4/008 ,  H01G4/06

CPC classification number: H01G4/228 ,  H01G2/065 ,  H01L2224/48091 ,  H01L2924/19107 ,  H05K3/328 ,  H05K3/341 ,  H05K2201/10643 ,  H05K2201/10659 ,  H05K2201/10909 ,  H05K2203/049 ,  H01L2924/00014

Abstract: A single layer ceramic capacitor for wire bonding or solder or epoxy attachment wherein a bottom metallization is of a lesser purity than a top metallization whereby the bottom metallization may be effectively soldered without leaching of the metal and the top metallization may be wire bonded. In an exemplary embodiment, the top metallization is essentially pure gold and the bottom metallization is an alloy of gold and platinum and/or palladium. The top and bottom metallizations are provided on a dielectric body that advantageously comprises a ceramic having a sintering temperature below the melting point of gold. In a further exemplary embodiment, the capacitance of the capacitor may be enhanced by providing one or more interior metallization planes parallel to the exterior metallizations and connected thereto by conductive vias.

Abstract translation: 用于引线接合或焊料或环氧树脂附着的单层陶瓷电容器，其中底部金属化的纯度比顶部金属化的纯度低，由此底部金属化可以有效地焊接而不会浸出金属，并且顶部金属化可以是引线键合的。 在示例性实施例中，顶部金属化基本上是纯金，底部金属化是金和铂和/或钯的合金。 顶部和底部金属化物提供在电介质体上，其有利地包括具有低于金熔点的烧结温度的陶瓷。 在另一示例性实施例中，可以通过提供一个或多个内部金属化平面平行于外部金属化并通过导电通孔与其连接的电容来增强电容器的电容。

公开(公告)号：US5740010A

公开(公告)日：1998-04-14

申请号：US528885

申请日：1995-09-15

Applicant: Daniel F. Devoe ,  Alan D. Devoe

Inventor： Daniel F. Devoe ,  Alan D. Devoe

IPC: H01G4/38 ,  H01L23/13 ,  H01G4/00

CPC classification number: H01L23/13 ,  H01G4/38 ,  H01G4/385 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48465 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15162 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: Metal, normally gold or platinum, is printed, and is adhered by a glass frit, on the top and/or bottom surfaces of a multi-layer laid-up green ceramic wafers containing typically up to 16 layers and 800+ separate devices, typically 800+ monolithic, buried-substrate, ceramic multiple capacitors. The wafer is diced, and the multiple ceramic capacitors each with its patterned surface metal are co-fired. The integrally formed, top and bottom surface, conduction traces connect similarly formed pads, typically disposed in a "pin-grid" pattern, to later-added side traces or conductive castellations that connect to the electrodes of multiple buried-substrate capacitors. The pads are precisely located, and extend over such ample areas, to support the stable surface mounting, and the reliable electrical connection of, diverse external electrical circuits and components. The surface mounting may be by and of adhering with conductive adhesive, soldering, reflow soldering, gold wire bonded, aluminum wire bonding, flip-chip mounting, die bonding and like processes, including automated processes. The pads on the bottom surface typically support mounting the ceramic multiple capacitor to a printed circuit board, flexible substrate, alumina substrate, multi-chip module or the like. Meanwhile, pads on the top surface typically support the physical mounting and electrical connection of one or more electrical circuits--including ICs--or components piggyback on top of the multiple capacitor, including in a dense three-dimensional multi-tier, tower, arrangement.

Abstract translation: 金属（通常是金或铂）被印刷并通过玻璃料粘附在多层铺设的绿色陶瓷晶片的顶部和/或底部表面上，所述多层铺设的生坯陶瓷晶片通常包含多达16层和800多种分离的装置，通常 800+单片，埋地衬底，陶瓷多电容器。 将晶片切割，并将多个陶瓷电容器与其图案化的表面金属共烧。 整体形成的顶部和底部表面，导电迹线将类似地形成的通常以“引脚格栅”图案设置的焊盘连接到连接到多个埋地衬底电容器的电极的稍后添加的侧面迹线或导电雉。。 焊盘精确定位，并延伸到这样丰富的区域，以支持稳定的表面安装，以及各种外部电路和组件的可靠电气连接。 表面安装可以通过导电粘合剂，焊接，回流焊接，金线接合，铝线接合，倒装芯片安装，管芯接合等并且包括自动化工艺的粘合。 底表面上的焊盘通常支持将陶瓷多电容器安装到印刷电路板，柔性衬底，氧化铝衬底，多芯片模块等上。 同时，顶表面上的焊盘通常支持一个或多个电路的物理安装和电连接，包括集成电路，或者多重电容器顶部上的部件，包括以致密的三维多层塔式结构。

公开(公告)号：US5625528A

公开(公告)日：1997-04-29

申请号：US528855

申请日：1995-09-15

Applicant: Daniel F. Devoe ,  Alan D. Devoe

Inventor： Daniel F. Devoe ,  Alan D. Devoe

IPC: H01G4/38 ,  H01L23/13 ,  H01G4/00 ,  H01G4/06 ,  H01G4/12

CPC classification number: H01G4/38 ,  H01G4/385 ,  H01L23/13 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15162 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: A monolithic, buried-substrate, ceramic multiple capacitor is laid up as multiple capacitors that are isolated, one to the next, by a dual-dielectric-constant, three-layer-laminate, isolation layer. Each isolation layer has and presents (i) an innermost layer of a low dielectric constant (low K) material, located between (ii) outer laminate layers of a high dielectric constant (high K) material. By such construction negative effects of the physio-chemical reaction (i) occurring at the boundary between the high-K and low-K layers, (ii) contaminating the high-K dielectric and lowering its K, and (iii) undesirably serving both to lower the capacitance of any (buried substrate) capacitor that makes use of the ("contaminated") high-K dielectric while increasing capacitor leakage current, are mitigated or avoided. This occurs because the physio-chemical reaction zone, or band, located between the high-K dielectric layers (from which each buried-substrate capacitor is formed) and the low-K dielectric isolation layer (between successive capacitors) is moved slightly away from the region of the capacitor itself. Moreover, the ceramic multiple capacitor is strongly and stably fused together in its several layers, which different layers of different dielectric constant have different thermal coefficients of expansion, because the outer (high-K) laminate layers of the isolation layer are preferably of intermediary thickness between the innermost (low-K) layer and the (high-K) dielectric layers of the bordering buried-substrate capacitors.

Abstract translation: 单片埋地衬底陶瓷多电容器被放置为通过双电介质常数三层层压隔离层隔离的多个电容器。 每个隔离层具有（i）位于（ii）高介电常数（高K）材料的外层叠层之间的低介电常数（低K）材料的最内层。 通过这样的结构，在高K和低K层之间的边界处产生的生理化学反应（i）的负面影响，（ii）污染高K电介质并降低其K，和（iii）不合需要地服务于 降低使用（“污染”）高K电介质同时增加电容器漏电流的任何（掩埋衬底）电容器的电容，得到缓解或避免。 这是因为位于高K电介质层（形成每个掩埋衬底电容器）和低K电介质隔离层（连续电容器之间）之间的物理化学反应区或带被略微远离 电容器本身的区域。 此外，由于隔离层的外（高K）层压层优选为中间厚度，所以陶瓷多电容器以其几层牢固稳定地熔合在一起，其中不同介电常数的不同层具有不同的热膨胀系数 在最内层（低K）层和边界掩埋衬底电容器的（高K）电介质层之间。

公开(公告)号：US06695940B2

公开(公告)日：2004-02-24

申请号：US09828558

申请日：2001-04-05

Applicant: Alan D. Devoe ,  Mary Trinh

Inventor： Alan D. Devoe ,  Mary Trinh

IPC: B32B3126

CPC classification number: B32B9/005 ,  B28B21/48 ,  B32B1/08 ,  B32B2457/18 ,  Y10T428/1317 ,  Y10T428/1321

Abstract: Very thin cast ceramic tape, preferably approximately 12 &mgr;m in thickness, is wrapped, preferably in a reversing spiral or helix, around a mandrel, preferably a mandrel made of steel and coated with a wax releasing agent, for so many times, preferably five or greater, as achieves a desired thickness of a tube wall, preferably about 100 &mgr;m. The green ceramic tube is then laminated in a pressure laminator, preferably a hydrostatic laminator at 3000 to 5000 psi, linking polymer chains between each ceramic layer, cross-linking polymer chains within each ceramic layer, and densifying the produced ceramic laminate tube by reducing porosity. By varying the wraps, wrapping and/or mandrel surface, high quality thin-wall laminate ceramic tubes having any of (i) external reinforcement windings as enhance burst strength, (ii) thickened end regions as facilitate mounting while reducing breakage, and/or (iii) internal features, including baffles, as desirably induce turbulence in longitudinal gas flow, may all readily be fabricated, including in an automated process.

Abstract translation: 优选约12μm厚的非常薄的铸造陶瓷带围绕心轴，优选由钢制成的心轴并用蜡脱模剂包裹，优选以反转的螺旋或螺旋缠绕多次，优选为5或 更优选地，达到期望的管壁厚度，优选约100μm。 然后将绿色陶瓷管层压在压力层压机中，优选在3000至5000psi的静液压层压机中，在每个陶瓷层之间连接聚合物链，在每个陶瓷层内连接交联聚合物链，并通过减少孔隙率致密化生产的陶瓷层压管 。 通过改变包裹，包裹和/或心轴表面，具有任何（i）外部加强绕组作为增强突出强度的高质量薄壁层压陶瓷管，（ii）加厚的端部区域，以便于安装同时减少断裂，和/或 （iii）内部特征，包括挡板，如期望地导致纵向气流中的湍流，可以容易地被制造，包括在自动化过程中。

公开(公告)号：US6081416A

公开(公告)日：2000-06-27

申请号：US87209

申请日：1998-05-28

Applicant: Hung Trinh ,  Alan D. Devoe ,  Daniel Devoe

Inventor： Hung Trinh ,  Alan D. Devoe ,  Daniel Devoe

IPC: H01G4/12 ,  H01G4/228 ,  H01G4/232 ,  H05K3/34 ,  H01G2/20

CPC classification number: H01G4/2325 ,  H01G4/12 ,  H01G4/228 ,  H01G4/232 ,  H05K3/3426

Abstract: A ceramic electrical device or component, normally a barium titanate ceramic capacitor, having a first coefficient of thermal expansion (CTE), typically about 10 parts per million per degree centigrade (10 ppm/.degree.C.), is physically and electrically mounted through an intermediary solder layer, normally copper, to a lead frame, normally made from a selected alloy of nickel-iron, having a second CTE at least one-fifth (20%) less, and more typically about 5 ppm/.degree.C., or one-half (50%) less, than is the CTE of the ceramic capacitor. Because ceramics are stronger in compression than in tension, the ceramic capacitor held within the lead frame is less likely to undergo a stress fracture at temperatures elevated above those of assembly than would be the case should the CTE's be equal, or should the CTE of the lead frame be greater than the CTE of the ceramic capacitor. Leaded ceramic capacitors, stacked multilayer ceramic capacitors, ceramic inductors and ceramic resistors so constructed satisfy United States standards for electronic components used in broad-temperature-range demanding military and space applications.

Abstract translation: 通常具有第一热膨胀系数（CTE）的陶瓷电气装置或部件，通常为钛酸钡陶瓷电容器，通常约为10ppm /摄氏度（10ppm /℃），通过以下方式物理和电气安装： 中间焊料层，通常为铜，通常由选择的镍 - 铁合金制成，具有第二CTE至少五分之一（20％），更通常约5ppm /℃的引线框，或 比陶瓷电容器的CTE少一半（50％）。 由于陶瓷的压缩强度比拉伸强度高，所以保持在引线框架内的陶瓷电容器在高于组装温度的温度下不太可能发生应力断裂，而不是CTE等于或者CTE 引线框架大于陶瓷电容器的CTE。 有铅陶瓷电容器，堆叠多层陶瓷电容器，陶瓷电感器和陶瓷电阻器的结构符合美国在宽温度要求苛刻的军事和空间应用中使用的电子元件的标准。

公开(公告)号：US6011684A

公开(公告)日：2000-01-04

申请号：US59742

申请日：1998-04-14

Applicant: Alan D. Devoe ,  Lambert T. Devoe

Inventor： Alan D. Devoe ,  Lambert T. Devoe

IPC: H01L23/13 ,  H01L23/498 ,  H01G4/38

CPC classification number: H01L23/13 ,  H01L23/49805 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15162 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025

Abstract: Variable width electrically conductive (i) traces and (ii) pads in the forms of castellations and connecting traces upon the surfaces of volume microminiature electronic components permit variable area electrical interconnection in three dimensions, particularly of monolithic, buried-substrate, multiple ceramic capacitors to integrated circuit receivers and amplifiers to make microminiature hearing aids insertable within the ear canal. A preferred embodiment monolithic multiple capacitor with side, top and bottom surfaces has a number of electrically conductive parallel layers disposed within its body with a conductive trace extending from each layer to be exposed upon a side surface. Metallized bus strips of at least two widths extend along the side surface; relatively thinner bus strips selectively interconnecting the exposed traces to form a plurality of capacitors while the relatively thicker bus strips selectively extend at least some traces to one or more edge(s) of the top and/or bottom surfaces of the body where they may be externally connected, normally to piggy-backed components, by reflow soldering. The different-width metallized bus strips are preferably made by rectangular saw-cut slots in the body at differently spaced intervals, the rectangular saw-cuts forming castellations having a greater depth than width to reduce parasitic capacitance.

Abstract translation: 可变宽度导电（i）迹线和（ii）体积微型电子部件表面上的蓖耳形式和连接迹线形式的焊盘允许三维的可变面积电互连，特别是单片，埋地衬底，多个陶瓷电容器 集成电路接收器和放大器，以使微型助听器可插入耳道内。 具有侧表面，顶表面和底表面的优选实施例的单片多电容器具有设置在其主体内的多个导电平行层，其中导电迹线从每个层延伸以暴露在侧表面上。 至少两个宽度的金属化母线沿着侧面延伸; 相对较薄的总线条选择性地互连暴露的迹线以形成多个电容器，而相对较厚的母线选择性地将至少一些迹线延伸到身体的顶部和/或底部表面的一个或多个边缘，在那里它们可以是 外部连接，通常通过回流焊接到猪背部件。 不同宽度的金属化母线条优选地以不同间隔的间隔在主体中由矩形锯切槽制成，矩形锯切形成具有比宽度更大的深度的窖以减小寄生电容。

公开(公告)号：US5657199A

公开(公告)日：1997-08-12

申请号：US528856

申请日：1995-09-15

Applicant: Daniel F. Devoe ,  Alan D. Devoe

Inventor： Daniel F. Devoe ,  Alan D. Devoe

IPC: H01G4/38 ,  H01L23/13

CPC classification number: H01G4/38 ,  H01G4/385 ,  H01L23/13 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15162 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: Leaded electrical circuits and components, typically receivers and amplifiers used in micro-miniature hearing aids, are closely physically mounted by their leads extending within laser-drilled through-holes, typically three such holes, to multiple buried-substrate capacitors within a monolithic ceramic multiple capacitor. Electrical connection to the leads does not transpire within the holes, but rather though soldered or like connection to conductive pads surrounding the holes and continuing first as circuit traces on the top of the monolith, and then as electrically-conductive trace or castellations on the sides of the monolith, until reaching electrodes of the buried-substrate capacitors patterned so as to be brought to side surfaces of the monolith. The direct electrical connection is normally to multiple plates of plural buried-substrate capacitors, typically including a relatively large, typically 1.0 .mu.farad, capacitor in electrical parallel with a smaller, typically 100 picofarads, capacitor. Both capacitances jointly serve as an effective filter to noise in two separate frequency bands, typically centered about 100 kHz and about 100 MHz.

Abstract translation: 带电的电路和组件，通常是微型助听器中使用的接收器和放大器，通过它们的引线紧密地物理地安装，这些引线在激光钻孔的通孔（通常为三个这样的孔）内延伸到单片陶瓷多重的多个埋地衬底电容器 电容器。 与引线的电气连接不会发生在孔内，而是通过焊接或类似于连接到围绕孔的导电焊盘并且首先连接到整体顶部上的电路迹线，然后作为导电迹线或侧壁上的导电迹线 直到到达掩模衬底电容器的电极被图案化以便被带到整体的侧表面。 直接电连接通常是多个埋地衬底电容器的多个板，通常包括与较小的，通常为100皮法的电容器电并联的相对较大的通常为1.0微法兰的电容器。 两个电容在两个分开的频带中共同作为有效的噪声滤波器，通常以100kHz和大约100MHz为中心。

公开(公告)号：US5367430A

公开(公告)日：1994-11-22

申请号：US964150

申请日：1992-10-21

Applicant: Alan D. DeVoe ,  Daniel F. DeVoe

Inventor： Alan D. DeVoe ,  Daniel F. DeVoe

IPC: H01G4/38 ,  H01L23/13

CPC classification number: H01L23/13 ,  H01G4/38 ,  H01L2224/32145 ,  H01L2924/09701 ,  H01L2924/15162 ,  Y10T29/435

Abstract: A monolithic multiple ceramic capacitor is made by interspersing layers of green tape containing ceramic powder in a binder with printed layers of electrical conductors, then compressing the layers and heating them to sinter the ceramic powder. Edge connections link the conducting layers in predetermined patterns to provide external connections to the capacitors. Use of parasitic or stray capacitance between pairs of external terminals provides additional useful values of capacitance. Unwanted stray capacitance between adjacent terminals is reduced by making slots by saw cuts or the like in either the green tape or the sintered material. Unwanted stray capacitance between elements inside the capacitor is reduced by ground planes between layers of capacitors and by layers of ceramic materials having relatively low dielectric constants to separate layers of capacitors, to form exterior layers of insulating material, or both.

Abstract translation: 单片多层陶瓷电容器是通过在粘合剂中将包含陶瓷粉末的生胶带层叠印刷电导体层，然后压缩层并加热它们以烧结陶瓷粉末而制成的。 边缘连接以预定模式连接导电层以提供到电容器的外部连接。 使用外部端子对之间的寄生或杂散电容提供额外的有用的电容值。 通过在生胶带或烧结材料中通过锯切等形成狭缝来减少相邻端子之间的杂散电容。 电容器内的元件之间的杂散电容通过电容器层之间的接地层和具有相对较低的介电常数的陶瓷材料层分开，以分离电容器层，以形成绝缘材料的外层或两者来减少。