公开(公告)号：US20090006779A1

公开(公告)日：2009-01-01

申请号：US11987879

申请日：2007-12-05

Applicant: Chien-Chou Chen ,  Bin Feng Hung ,  Chi-Chang Lu

Inventor： Chien-Chou Chen ,  Bin Feng Hung ,  Chi-Chang Lu

IPC: G06F12/00

CPC classification number: G06F13/1689

Abstract: The invention discloses a memory control system and a method to read data from memory. The memory control system comprises a control unit, a storage device, and a microprocessor. The memory control system and the method to read data from memory according to the invention utilize an unbalanced microprocessor clock signal with different duration length to control the microprocessor so as to increase the speed of reading memory.

Abstract translation: 本发明公开了一种从存储器读取数据的存储器控​​制系统和方法。 存储器控制系统包括控制单元，存储设备和微处理器。 根据本发明的存储器控​​制系统和从存储器读取数据的方法利用具有不同持续时间长度的不平衡微处理器时钟信号来控制微处理器以增加读取存储器的速度。

公开(公告)号：US07861045B2

公开(公告)日：2010-12-28

申请号：US11987879

申请日：2007-12-05

Applicant: Chien-Chou Chen ,  Bin Feng Hung ,  Chi-Chang Lu

Inventor： Chien-Chou Chen ,  Bin Feng Hung ,  Chi-Chang Lu

IPC: G06F12/00

CPC classification number: G06F13/1689

Abstract: The invention discloses a memory control system and a method to read data from memory. The memory control system comprises a control unit, a storage device, and a microprocessor. The memory control system and the method to read data from memory according to the invention utilize an unbalanced microprocessor clock signal with different duration length to control the microprocessor so as to increase the speed of reading memory.

Abstract translation: 本发明公开了一种从存储器读取数据的存储器控​​制系统和方法。 存储器控制系统包括控制单元，存储设备和微处理器。 根据本发明的存储器控​​制系统和从存储器读取数据的方法利用具有不同持续时间长度的不平衡微处理器时钟信号来控制微处理器以增加读取存储器的速度。

公开(公告)号：US20090125761A1

公开(公告)日：2009-05-14

申请号：US12116208

申请日：2008-05-07

Applicant: Wen-Min Lu ,  Bin-Feng Hung ,  Ming-Sung Huang

Inventor： Wen-Min Lu ,  Bin-Feng Hung ,  Ming-Sung Huang

IPC: G11C29/04

CPC classification number: G11C29/70

Abstract: A method for controlling a DRAM includes detecting failed memory cells of the DRAM, recording the rows corresponding to the failed memory cells, receiving a control signal for accessing the memory cell with column address X and row address Y, determining if the row address Y is in the recorded failed rows list, and if yes, replacing the memory cell to be accessed with the memory cell with the column address X and row address Z which is not same as Y.

Abstract translation: 用于控制DRAM的方法包括检测DRAM的故障存储单元，记录与故障存储单元相对应的行，接收用列地址X和行地址Y访问存储单元的控制信号，确定行地址Y是否为 在记录的失败行列表中，如果是，则使用不同于Y的列地址X和行地址Z替换要访问的存储单元。