公开(公告)号：US5880970A

公开(公告)日：1999-03-09

申请号：US824086

申请日：1997-03-24

Applicant: Ranko Scepanovic ,  Cheng-Liang Ding

Inventor： Ranko Scepanovic ,  Cheng-Liang Ding

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: An apparatus and method for locating a good approximation of optimal Steiner tree routing in the presence of rectilinear obstacles, including finding a Steiner tree on an escape graph. The escape graph is constructed by forming lines from given points (pins) and obstacles. Obstacles and the segments of obstacles are provided with lines parallel to that segment at a given minimum distance S.sub.min from the obstacle is constructed until it reaches either a boundary of an obstacle or a boundary of the core. For pins which do belong to a boundary of an obstacle, a ray, perpendicular to the segment of the boundary on which the pin is located is constructed from the pin and out from the obstacle until it reaches another obstacle or a boundary of the core. For pins which do not belong to an obstacle, vertical and horizontal lines are constructed. A Steiner tree may then be found on the escape graph by using any number of algorithms such as algorithm S and algorithm M. The solution to the problem of finding a Steiner tree for the escape graph also provides a suitable approximation of a Steiner tree for the original problem. This apparatus or method may be used to optimize the routing of conductive paths on integrated circuits.

Abstract translation: 一种用于在存在直线障碍物的情况下定位最佳Steiner树路由的良好近似的装置和方法，包括在逃逸图上找到Steiner树。 通过从给定点（针）和障碍物形成线来构造逃生图。 障碍物和障碍物段在距障碍物的给定最小距离Smin处被构造成直到到达障碍物的边界或核心的边界为止，与该段平行的线条被提供。 对于属于障碍物边界的引脚，垂直于引脚所在边界的段的射线由引脚构成，并从障碍物中出来，直至到达核心的另一个障碍物或边界。 对于不属于障碍物的引脚，构建垂直和水平线。 然后可以通过使用任何数量的算法（例如算法S和算法M）在转义图上找到Steiner树。为逃逸图找到Steiner树的问题的解决方案也为Steiner树提供了合适的近似， 原来的问题。 该装置或方法可用于优化集成电路上的导电路径的路由。

公开(公告)号：US5801959A

公开(公告)日：1998-09-01

申请号：US713597

申请日：1996-09-12

Applicant: Cheng-Liang Ding ,  Jiabi J. Zhu

Inventor： Cheng-Liang Ding ,  Jiabi J. Zhu

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: The invention quickly produces a dense layout for an integrated circuit that enables a smaller die to be used to implement the integrated circuit than would otherwise be the case, resulting in a desirable size reduction in the final packaged integrated circuit. The invention combines routing space estimation and adjustment (a technique similar to channel-based global routing) with area-based detailed routing, resulting in an approach that provides the benefits of both channel-based and area-based layout techniques while minimizing the disadvantages of those techniques.

Abstract translation: 本发明快速地产生用于集成电路的致密布局，其使得能够使用较小的管芯来实现集成电路，而不是其他情况，导致最终封装集成电路中所需的尺寸减小。 本发明将路由空间估计和调整（类似于基于信道的全局路由的技术）与基于区域的详细路由相结合，导致提供基于信道和面向布局技术的优点的方法，同时最小化 那些技术。

公开(公告)号：US5566078A

公开(公告)日：1996-10-15

申请号：US68013

申请日：1993-05-26

Applicant: Cheng-Liang Ding ,  Ching-Yen Ho

Inventor： Cheng-Liang Ding ,  Ching-Yen Ho

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: An integrated circuit layout technique is described which employs an optimization-driven clustering technique to provide improved cell placement. The technique utilizes clustering of cells based upon Rent's rule, with global-optimization-derived inter-cell distances being used to break ties when identical Rent exponents are encountered. A constraint on the number of cells permitted to be in a cluster and a constraint on the maximum Rent exponent which to be considered for merging clusters minimize the "overgrowth" of clusters and serve to even out cluster size, ideally suiting the technique to conventional partitioning and placement schemes.

Abstract translation: 描述了采用优化驱动的聚类技术来提供改进的单元布局的集成电路布局技术。 该技术基于租金规则利用单元格聚类，当遇到相同的租金指数时，使用全局优化导出的单元间距离来破坏关系。 对于允许在集群中的单元数量的约束以及对于合并集群要考虑的最大租金指数的约束，可以最大限度地减少集群的“过度增长”，并且用于均匀集群大小，理想地将该技术适用于常规分区 和安置计划。

公开(公告)号：US5682321A

公开(公告)日：1997-10-28

申请号：US318275

申请日：1994-10-05

Applicant: Cheng-Liang Ding ,  Ting-Chi Wang ,  Mary Jane Irwin

Inventor： Cheng-Liang Ding ,  Ting-Chi Wang ,  Mary Jane Irwin

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A large number of microelectronic circuit cells that are interconnected by a set of wiring nets are optimally placed on an integrated circuit chip such that all interconnects can be routed and the total wirelength of the interconnects is minimized. Cells are first grouped into disjoint clusters by an optimization-driven clustering technique, which uses both local and global connectivity information among the cells. This technique uses Rent's rule for combining pairs of neighboring clusters, and selects among pairs of clusters having the same Rent's exponent using distance information derived from global optimization processing. Clusters are prevented from growing to an excessive size by limiting the number of cells per cluster and the maximum area per cluster to predetermined maximum values. After the clusters are generated, they are placed using an optimization-driven placement technique, preferably "Gordian". Finally, the cells within each cluster are de-clustered and locally placed using a partitioning technique, preferably "min-cut".

Abstract translation: 通过一组接线网互连的大量微电子电路单元被最佳地放置在集成电路芯片上，使得所有的互连可被路由并且互连的总线长度被最小化。 细胞首先通过优化驱动的聚类技术分组成不相交的聚类，其在小区中使用本地和全局连通性信息。 该技术使用租金规则来组合相邻群组，并且使用从全局优化处理得到的距离信息来选择具有相同租金指数的群集。 通过将每个簇的单元数量和每个簇的最大面积限制为预定的最大值，防止集群增长到过大的大小。 在生成簇之后，使用优化驱动的放置技术（最好是“Gordian”）来放置它们。 最后，使用分割技术，优选地“最小切割”，使每个簇内的单元被去聚集和局部放置。

公开(公告)号：US5615128A

公开(公告)日：1997-03-25

申请号：US599764

申请日：1996-02-12

Applicant: Ranko Scepanovic ,  Cheng-Liang Ding

Inventor： Ranko Scepanovic ,  Cheng-Liang Ding

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: An apparatus and method for locating a good approximation of optimal Steiner tree routing in the presence of rectilinear obstacles, including finding a Steiner tree on an escape graph. The escape graph is constructed by forming lines from given points (pins) and obstacles. Obstacles and the segments of obstacles are provided with lines parallel to that segment at a given minimum distance s.sub.min from the. The lines are constructed until they reaches either a boundary of an obstacle or a boundary of the core. For pins which do belong to a boundary of an obstacle, a ray, perpendicular to the segment of the boundary on which the pin is located is constructed from the pin and out from the obstacle until it reaches another obstacle or a boundary of the core. For pins which do not belong to an obstacle, vertical and horizontal lines are constructed. A Steiner tree may then be found on the escape graph by using any number of algorithms such as algorithm S and algorithm M. The solution to the problem of finding a Steiner tree for the escape graph also provides a suitable approximation of a Steiner tree for the original problem. This apparatus or method may be used to optimize the routing of conductive paths on integrated circuits.

Abstract translation: 一种用于在存在直线障碍物的情况下定位最佳Steiner树路由的良好近似的装置和方法，包括在逃逸图上找到Steiner树。 通过从给定点（针）和障碍物形成线来构造逃生图。 障碍物和障碍物段在距离该给定最小距离smin处具有与该段平行的线。 这些线被构造成直到它们到达障碍物的边界或者核心的边界。 对于属于障碍物边界的引脚，垂直于引脚所在边界的段的射线由引脚构成，并从障碍物中出来，直至到达核心的另一个障碍物或边界。 对于不属于障碍物的引脚，构建垂直和水平线。 然后可以通过使用任何数量的算法（例如算法S和算法M）在转义图上找到Steiner树。为逃逸图找到Steiner树的问题的解决方案也为Steiner树提供了合适的近似， 原来的问题。 该装置或方法可用于优化集成电路上的导电路径的路由。

公开(公告)号：US5491641A

公开(公告)日：1996-02-13

申请号：US131770

申请日：1993-10-04

Applicant: Ranko Scepanovic ,  Cheng-Liang Ding

Inventor： Ranko Scepanovic ,  Cheng-Liang Ding

IPC: G06F17/50 ,  G06F15/00

CPC classification number: G06F17/5077

Abstract: An apparatus and method for locating a good approximation of optimal Steiner tree routing in the presence of rectilinear obstacles, including finding a Steiner tree on an escape graph. The escape graph is constructed by forming lines from given points (pins) and obstacles. Obstacles and the segments of obstacles are provided with lines parallel to that segment at a given minimum distance S.sub.min from the obstacle. The lines are constructed until they reach either a boundary of an obstacle or a boundary of the core. For pins which do belong to a boundary of an obstacle, a ray, perpendicular to the segment of the boundary on which the pin is located is constructed from the pin and out from the obstacle until it reaches another obstacle or a boundary of the core. For pins which do not belong to an obstacle, vertical and horizontal lines are constructed. A Steiner tree may then be found on the escape graph by using any number of algorithms such as algorithm S and algorithm M. The solution to the problem of finding a Steiner tree for the escape graph also provides a suitable approximation of a Steiner tree for the original problem. This apparatus or method may be used to optimize the routing of conductive paths on integrated circuits.

Abstract translation: 一种用于在存在直线障碍物的情况下定位最佳Steiner树路由的良好近似的装置和方法，包括在逃逸图上找到Steiner树。 通过从给定点（针）和障碍物形成线来构造逃生图。 在障碍物给定的最小距离Smin处，障碍物和障碍物段具有与该段平行的线。 这些线被构造成直到它们到达障碍物的边界或者核心的边界。 对于属于障碍物边界的引脚，垂直于引脚所在边界的段的射线由引脚构成，并从障碍物中出来，直至到达核心的另一个障碍物或边界。 对于不属于障碍物的引脚，构建垂直和水平线。 然后可以通过使用任何数量的算法（例如算法S和算法M）在转义图上找到Steiner树。为逃逸图找到Steiner树的问题的解决方案也为Steiner树提供了合适的近似， 原来的问题。 该装置或方法可用于优化集成电路上的导电路径的路由。