公开(公告)号：US07176137B2

公开(公告)日：2007-02-13

申请号：US10435009

申请日：2003-05-09

Applicant: Baw-Ching Perng ,  Yih-Shung Lin ,  Ming-Ta Lei ,  Ai-Sen Liu ,  Chia-Hui Lin ,  Cheng-Chung Lin

Inventor： Baw-Ching Perng ,  Yih-Shung Lin ,  Ming-Ta Lei ,  Ai-Sen Liu ,  Chia-Hui Lin ,  Cheng-Chung Lin

IPC: H01L21/302

CPC classification number: H01L29/6656 ,  H01L21/823468

Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

Abstract translation: 形成多个栅极侧壁间隔物的方法，每个栅极侧壁间隔件包括不同的相关栅极侧壁间隔物宽度，包括提供第一多个栅极结构; 在第一多个栅极结构上覆盖沉积第一介电层; 在第一介电层上铺设第二介电层; 通过第一和第二介电层的厚度回蚀; 覆盖沉积第一光致抗蚀剂层以覆盖第一多个并且图案化以选择性地暴露至少第二多个栅极结构; 对所述至少第二多个栅极结构进行各向同性蚀刻预定的时间段以选择性地蚀刻掉所述第一介电层的预定部分; 并且选择性地蚀刻掉第二介电层以留下包括多个相关联的侧壁间隔物宽度的栅极结构。

公开(公告)号：US06875655B2

公开(公告)日：2005-04-05

申请号：US10802564

申请日：2004-03-17

Applicant: Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

Inventor： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

IPC: H01L21/02 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/0207 ,  H01L27/10817 ,  H01L28/91

Abstract: A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

Abstract translation: 实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。 该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。 在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。 然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案以在电容器之间提供保护性层间电介质结构。 保护结构可防止在后续处理期间损坏底部电极。 蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。 在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

公开(公告)号：US20050004806A1

公开(公告)日：2005-01-06

申请号：US10601164

申请日：2003-06-20

Applicant: Dah-Chih Lin ,  Jeffrey Liou ,  Joseph Du ,  Chia-Hui Lin ,  Shih-Wen Tu ,  Hsien_Ying Tseng ,  Chun Chen ,  Yueh-Ching Lee

Inventor： Dah-Chih Lin ,  Jeffrey Liou ,  Joseph Du ,  Chia-Hui Lin ,  Shih-Wen Tu ,  Hsien_Ying Tseng ,  Chun Chen ,  Yueh-Ching Lee

IPC: G06F17/27 ,  G06Q10/00 ,  G06F17/60

CPC classification number: G06F17/2785 ,  G06F17/2775 ,  G06Q10/10 ,  G06Q50/184

Abstract: A method of analyzing a claim in a patent or patent application is disclosed, comprising retrieving a patent claim which has been rendered into a format parsable by a computer program into a computer memory; parsing the claim into a set of discrete elements; categorizing each element in the set of elements according to a predetermined rule; and storing a set of categorized elements in a data store. A parsing program executable in a computer may be used to parse the patent claim and, optionally, to identify one or more keyword sets in the parsed claim. A rating program may also be used to assign a rating weight to each categorized element. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract translation: 公开了一种分析专利或专利申请中的权利要求的方法，包括将已经呈现为可由计算机程序解析的格式的专利权利要求检索到计算机存储器中; 将声明解析成一组离散元素; 根据预定规则对元素集合中的每个元素进行分类; 并将一组分类元素存储在数据存储中。 可以使用计算机中可执行的解析程序来解析专利权利要求，并且可选地，用于识别解析的权利要求中的一个或多个关键字集合。 评级程序也可用于为每个分类元素分配评级权重。 要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US06746900B1

公开(公告)日：2004-06-08

申请号：US10369992

申请日：2003-02-19

Applicant: Ai-Sen Liu ,  Baw-Ching Perng ,  Ming-Ta Lei ,  Wen-Kai Wan ,  Cheng-Chung Lin ,  Kuei-Wu Huang ,  Yih-Shung Lin ,  Chia-Hui Lin

Inventor： Ai-Sen Liu ,  Baw-Ching Perng ,  Ming-Ta Lei ,  Wen-Kai Wan ,  Cheng-Chung Lin ,  Kuei-Wu Huang ,  Yih-Shung Lin ,  Chia-Hui Lin

IPC: H01L21335

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/66583

Abstract: In a method of forming an integrated circuit, a sacrificial layer is formed over a substrate. The sacrificial layer has a gate trench formed therein and a first layer of a first material formed over the substrate in the gate trench. A second layer of a second material is formed over the first layer in the gate trench. The first and second layers are processed to form a layer of a high-K dielectric material.

Abstract translation: 在形成集成电路的方法中，在衬底上形成牺牲层。 牺牲层具有形成在其中的栅极沟槽和形成在栅极沟槽中的衬底上的第一材料的第一层。 第二材料的第二层形成在栅极沟槽中的第一层上。 处理第一层和第二层以形成高K电介质材料层。

公开(公告)号：US06586142B1

公开(公告)日：2003-07-01

申请号：US09408702

申请日：1999-09-30

Applicant: Chia-Hui Lin ,  Chun Ming Wang

Inventor： Chia-Hui Lin ,  Chun Ming Wang

IPC: G03F900

CPC classification number: G03F1/36 ,  G03F1/70 ,  G03F7/2022 ,  G03F7/70466

Abstract: A process to correct distortions due to optical proximity effects is described. A two reticle per pattern approach is used. The first, or primary, reticle contains the image that is to be transferred to the photoresist. It is used to expose the resist in the usual way to the correct dosage of light needed to optimally activate it. For a primary reticle bearing a line pattern, the second, or correction, reticle bears a pattern of rectangles which are located and dimensioned so that, when aligned relative to the primary reticle, they overlap all line ends in the pattern. The amount by which the rectangles overlap the lines is similar to the amount by which serifs (if they had been used) would overlap. The amount by which the rectangles extend outside the line ends is not critical (provided it is at least as large as the inside overlap amount). This property allows a single rectangle to be shared by many line ends. After the first exposure, the correction reticle is substituted for the primary reticle and, after alignment, a second, much shorter, exposure is given. The resist is then developed in the normal way, resulting in a patterned etch mask that is largely free of distortion. A similar approach applies to hole patterns except that a positive resist must be used.

Abstract translation: 描述了由于光学邻近效应而校正失真的过程。 使用两个分划板每个图案方法。 第一或主要的掩模版包含要转移到光致抗蚀剂的图像。 它用于以通常的方式将抗蚀剂暴露于最佳激活所需的正确剂量的光。 对于具有线图案的主要掩模版，第二或修正的掩模版具有定位和尺寸的矩形图案，使得当相对于主掩模版对准时，它们与图案中的所有线端重叠。 矩形与线重叠的量与衬线（如果已被使用）重叠的量相似。 矩形在线端部外延伸的量不是关键的（只要它至少与内部重叠量一样大）。 此属性允许单个矩形由许多行末端共享。 在第一次曝光之后，校正掩模版代替初级掩模版，并且在对准之后，给出第二次短得多的曝光。 然后以正常方式显影抗蚀剂，得到大部分没有变形的图案化蚀刻掩模。 类似的方法适用于孔图案，除了必须使用正性抗蚀剂。

公开(公告)号：US06301698B1

公开(公告)日：2001-10-09

申请号：US09387434

申请日：1999-09-01

Applicant: Chia-Hui Lin ,  San-De Tzu

Inventor： Chia-Hui Lin ,  San-De Tzu

IPC: G06F1750

CPC classification number: G03F1/32 ,  G03F1/29 ,  G03F1/34

Abstract: A method is described for using computer aided design data for contact holes in a background, such as an opaque background or a phase shifting background, to generate computer aided design data for fabricating a mask an outrigger pattern. The outrigger pattern mask has contact holes surrounded by a first border of opaque material and the first border of opaque material surrounded by a third border of attenuating or 100% transmittance phase shifting material. The third border of attenuating or 100% transmittance phase shifting material is surrounded by opaque material. The design data for the contact hole pattern, a background pattern, a first correction pattern, and a second correction pattern are combined in a computer processor to generate final data. The final data is used to fabricate the mask.

Abstract translation: 描述了一种方法，用于使用计算机辅助设计数据用于背景中的接触孔，例如不透明背景或相移背景，以产生用于制造掩模外伸支架图案的计算机辅助设计数据。 外伸支架图案掩模具有被不透明材料的第一边界包围的接触孔和由衰减或100％透射相移材料的第三边界包围的不透明材料的第一边界。 衰减或100％透光相移材料的第三个边界被不透明材料包围。 接触孔图案的设计数据，背景图案，第一校正图案和第二校正图案被组合在计算机处理器中以产生最终数据。 最终的数据用于制作掩码。

公开(公告)号：US06174801B1

公开(公告)日：2001-01-16

申请号：US09261997

申请日：1999-03-05

Applicant: San-De Tzu ,  Ching-Shiun Chiu ,  Chia-Hui Lin

Inventor： San-De Tzu ,  Ching-Shiun Chiu ,  Chia-Hui Lin

IPC: H01L214763

CPC classification number: H01L21/76807 ,  G03F7/2059 ,  H01L21/02063 ,  H01L21/0277 ,  H01L21/3081 ,  H01L21/3086 ,  H01L2221/1021

Abstract: A method is disclosed for employing direct electron beam writing in the lithography used for forming step-profiles in semiconductor devices. The number of steps in the profiles are not limited. An electron beam sensitive resist is formed over a substrate. The resist is then exposed to a scanning electron beam having precise information, including proximity effect correction data, to directly form stair-case-like openings in the resist. The highly accurately dimensioned step-profiles are then transferred into the underlying layers by performing appropriate etchings. The resulting structures are shown to be especially suitable for forming damascene interconnects for submicron technologies.

Abstract translation: 公开了一种在用于在半导体器件中形成阶梯轮廓的光刻中采用直接电子束写入的方法。 配置文件中的步骤数不受限制。 在衬底上形成电子束敏感抗蚀剂。 然后将抗蚀剂暴露于具有精确信息的扫描电子束，包括邻近效应校正数据，以直接在抗蚀剂中形成阶梯状开口。 然后通过执行适当的蚀刻将高度精确尺寸的阶梯轮廓转移到下面的层中。 所得到的结构显示出特别适用于形成亚微米技术的镶嵌互连。

公开(公告)号：US5717427A

公开(公告)日：1998-02-10

申请号：US506959

申请日：1995-07-28

Applicant: Chia-Hui Lin

Inventor： Chia-Hui Lin

IPC: G06F3/033 ,  G09G5/08

CPC classification number: G06F3/03543 ,  G06F3/0312

Abstract: An optical-reflecting decoder modular design mechanism of mouse which is all components of mouse control circuit to adhere to the PCB using SMT technic, and this PCB is installed on a base which has two small size slotted discs, one ball member and one idle roller. Besides, the end of mouse cable has a connector which has several slots on the top center, and each slot has a connecting spring, and at the end of each spring has a connecting protuberance in order to touch to the touching point of the PCB. Also two sets of LED and phototransistors are adhered to the back of PCB, and installed reflecting lens under each LED and phototransistor, and install on the rack of two lens in a proper slope angle for light reflection.

Abstract translation: 一种光学反射解码器模块化设计机制，鼠标控制电路的所有组件都使用SMT技术粘贴在PCB上，该PCB安装在基座上，该基座上有两个小尺寸的开槽盘，一个球形件和一个空转辊 。 此外，鼠标电缆的端部具有在顶部中心具有多个槽的连接器，并且每个槽具有连接弹簧，并且在每个弹簧的端部具有连接突起以便接触PCB的接触点。 还有两套LED和光电晶体管粘贴在PCB的背面，并在每个LED和光电晶体管下安装反射镜，并以适当的倾斜角安装在两个镜头的机架上进行光反射。

公开(公告)号：US4977397A

公开(公告)日：1990-12-11

申请号：US427681

申请日：1989-10-13

Applicant: Wen-Chieh Kuo ,  Chia-Hui Lin ,  Te-Chang Chou ,  Yuan-Hsiung Liang

Inventor： Wen-Chieh Kuo ,  Chia-Hui Lin ,  Te-Chang Chou ,  Yuan-Hsiung Liang

IPC: G06F1/16 ,  G06F3/033 ,  G06F3/045

CPC classification number: G06F3/03547 ,  G06F1/1632 ,  G06F3/045

Abstract: A touch-control mouse provides rapid and accurate control of the positioning of a cursor on a computer display screen, and includes a laminated touch-control film assembly, an aluminum supporting board, a press button switch set, a signal processing circuit board, and a dust-protective hanging case. Drawing using a finger on x-axis and y-axis resistance planes of the laminated touch-control film assembly results in variable potential value for x, y coordinates. The value of potential variation is calculated through a single-chip microprocessor to indicate relative direction, speed and amount of displacement on x, y coordinates. The signal of the relative direction, speed and amount of displacement is further is further sent by the single-chip microprocessor through a standard RS-232 connector to one of the serial communications ports of a PC to rapidly and accurately control the positioning of the cursor on the computer display screen.

Abstract translation: 触摸控制鼠标可以快速准确地控制计算机显示屏幕上光标的定位，并且包括层叠的触摸控制膜组件，铝支撑板，按钮开关组，信号处理电路板和 防尘吊箱。 使用手指在层叠的触摸控制膜组件的x轴和y轴电阻平面上绘制导致x，y坐标的可变电位值。 通过单片微处理器计算电位变化的值，以指示x，y坐标上的相对方向，速度和位移量。 相对方向，速度和位移量的信号进一步由单片微处理器通过标准RS-232连接器发送到PC的串行通信端口之一，以快速，准确地控制光标的定位 在电脑显示屏幕上。

公开(公告)号：US08053894B2

公开(公告)日：2011-11-08

申请号：US11213238

申请日：2005-08-26

Applicant: Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Ta Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

Inventor： Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Ta Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

IPC: H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76886

Abstract: Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

Abstract translation: 用于形成半导体结构的装置，其包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。 导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层） 相互作用形成合金层。 合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。