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    High-performance hybrid processor with configurable execution units
    3.
    发明申请
    High-performance hybrid processor with configurable execution units 有权
    具有可配置执行单元的高性能混合处理器

    公开(公告)号：US20050166038A1

    公开(公告)日：2005-07-28

    申请号：US10120849

    申请日：2002-04-10

    Applicant: Albert Wang ,  Christopher Rowen ,  Bernard Rosenthal

    Inventor： Albert Wang ,  Christopher Rowen ,  Bernard Rosenthal

    IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/78 ,  G06F17/50 ,  H03K19/173 ,  G06F9/44

    CPC classification number: G06F9/30145 ,  G06F9/30181 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3867 ,  G06F9/3897 ,  G06F15/7867

    Abstract: A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and designed by automatic and semi-automatic methods. Improved reconfigurable execution units support deep pipelining, addition of additional registers and register files, compound instructions with many source and destination registers and wide data paths. New interface methods allow lower latency, higher bandwidth connections between hybrid processors and other logic.

    Abstract translation: 用于构建混合处理器的新一般方法通过允许在可重配置逻辑中实现更强大，紧密耦合的指令集扩展来实现应用中的更高性能。 可以通过自动和半自动方法发现和设计新的指令集配置。 改进的可重配置执行单元支持深度流水线，添加附加寄存器和寄存器文件，具有许多源和目标寄存器的复合指令以及宽数据路径。 新的接口方法允许混合处理器和其他逻辑之间的较低延迟，更高带宽连接。

    Translation lookaside buffer shutdown scheme
    4.
    发明授权
    Translation lookaside buffer shutdown scheme 失效
    翻译后备缓冲区关机方案

    公开(公告)号：US5325507A

    公开(公告)日：1994-06-28

    申请号：US19541

    申请日：1993-02-18

    Applicant: Danny L. Freitas ,  Craig C. Hansen ,  Christopher Rowen

    Inventor： Danny L. Freitas ,  Craig C. Hansen ,  Christopher Rowen

    IPC: G06F11/00 ,  G06F11/07 ,  G06F12/10 ,  G06F12/16

    CPC classification number: G06F11/073 ,  G06F11/004 ,  G06F11/0751 ,  G06F12/1045 ,  G06F11/076

    Abstract: An apparatus for temporarily disabling a translation lookaside buffer in a computer system upon the occurrence of certain predefined system conditions. Such conditions may be of a first type which have been predetermined to indicate a greater risk that two or more virtual addresses stored in the TLB will simultaneously match the incoming virtual address, and/or of a second type in which access to the TLB is not needed. An example of the first type is a reference to an unmapped segment of memory. An example of the second type is the processing of a non-memory-access instruction. The apparatus may further include failsafe circuitry to shut down the TLB if at least a given number of matches occur at any time and for any reason, the given number being greater than 1. The apparatus prevents loss of data or damage to the chip where match comparisons are performed in parallel.

    Abstract translation: 一种用于在发生某些预定义的系统条件时暂时禁用计算机系统中的翻译后备缓冲器的装置。 这样的条件可以是已经被预先确定的第一类型，以表示存储在TLB中的两个或更多个虚拟地址将同时匹配进入的虚拟地址，和/或其中对TLB的访问不是的第二类型的更大的风险 需要的 第一种类型的示例是对未映射的内存段的引用。 第二种类型的示例是非存储器访问指令的处理。 如果至少给定数量的匹配发生在任何时间，并且出于任何原因，给定数量大于1，则该装置还可以包括故障安全电路来关闭TLB。该装置防止丢失数据或损坏芯片，其中匹配 并行执行比较。

    Method for delivering free gift and advertising
    6.
    发明申请
    Method for delivering free gift and advertising 审中-公开
    提供免费礼品和广告的方法

    公开(公告)号：US20070038584A1

    公开(公告)日：2007-02-15

    申请号：US11201808

    申请日：2005-08-12

    Applicant: Christopher Faris ,  Eric McNiff ,  Christopher Rowen

    Inventor： Christopher Faris ,  Eric McNiff ,  Christopher Rowen

    IPC: G06Q30/00

    CPC classification number: G06Q30/02 ,  G06Q99/00

    Abstract: Sanitary free gifts are delivered in a sealed container to children located at points of giving frequented by children. The container contains collateral material such as advertisements, coupons or free samples directed to appeal and educate the children, parents or guardians of the children. The delivery system is designed to provide the provider of the collateral material experiences an increase in amounts of business in providing goods and/or services to the children, patents and/or guardians of the child for the supplier of the gifts and a benefit to the suppliers of the collateral material.

    Abstract translation: 卫生免费礼品通过密封的容器运送到儿童经常出门的儿童身上。 该容器包含诸如广告，优惠券或免费样品等辅助材料，用于上诉，并教育孩子的孩子，家长或监护人。 交付系统的设计是为了提供担保材料的提供者，为儿童供应商的孩子，专利和/或监护人提供货物和/或服务的业务量增加，并为其提供益处 供应商的辅助材料。

    High data density RISC processor
    8.
    发明授权
    High data density RISC processor 有权
    高数据密度RISC处理器

    公开(公告)号：US06282633B1

    公开(公告)日：2001-08-28

    申请号：US09192395

    申请日：1998-11-13

    Applicant: Earl A. Killian ,  Ricardo E. Gonzalez ,  Ashish B. Dixit ,  Monica Lam ,  Walter D. Lichtenstein ,  Christopher Rowen ,  John C. Ruttenberg ,  Robert P. Wilson

    Inventor： Earl A. Killian ,  Ricardo E. Gonzalez ,  Ashish B. Dixit ,  Monica Lam ,  Walter D. Lichtenstein ,  Christopher Rowen ,  John C. Ruttenberg ,  Robert P. Wilson

    IPC: G06K930

    CPC classification number: G06F9/30178 ,  G06F9/30145 ,  G06F9/30167

    Abstract: A RISC processor implements an instruction set which, in addition to optimizing a relationship between the number of instructions required for execution of a program, clock period and average number of clocks per instruction, also is designed to optimize the equation S=IS * BI, where S is the size of program instructions in bits, IS is the static number of instructions required to represent the program (not the number required by an execution) and BI is the average number of bits per instruction. Compared to conventional RISC architectures, this processor lowers both BI and IS with minimal increases in clock period and average number of clocks per instruction. The processor provides good code density in a fixed-length high-performance encoding based on RISC principles, including a general register with load/store architecture. Further, the processor implements a simple variable-length encoding that maintains high performance.

    Abstract translation: RISC处理器实现指令集，除了优化执行程序所需的指令数，时钟周期和每个指令的平均时钟数之间的关系外，还设计用于优化方程S = IS * BI， 其中S是以位为单位的程序指令的大小，IS是表示程序所需的指令的静态数量（而不是执行所需的数目），BI是每个指令的平均位数。 与传统的RISC体系结构相比，该处理器降低了BI和IS，时钟周期和每个指令的平均时钟周期几乎没有增加。 处理器在基于RISC原理的固定长度高性能编码中提供了良好的代码密度，包括具有加载/存储架构的通用寄存器。 此外，处理器实现了保持高性能的简单可变长度编码。

    High-performance hybrid processor with configurable execution units
    10.
    发明授权
    High-performance hybrid processor with configurable execution units 有权
    具有可配置执行单元的高性能混合处理器

    公开(公告)号：US07200735B2

    公开(公告)日：2007-04-03

    申请号：US10120849

    申请日：2002-04-10

    Applicant: Albert Wang ,  Christopher Rowen ,  Bernard Rosenthal

    Inventor： Albert Wang ,  Christopher Rowen ,  Bernard Rosenthal

    IPC: G06F15/80 ,  G06F9/44

    CPC classification number: G06F9/30145 ,  G06F9/30181 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3867 ,  G06F9/3897 ,  G06F15/7867

    Abstract: A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and designed by automatic and semi-automatic methods. Improved reconfigurable execution units support deep pipelining, addition of additional registers and register files, compound instructions with many source and destination registers and wide data paths. New interface methods allow lower latency, higher bandwidth connections between hybrid processors and other logic.

    Abstract translation: 用于构建混合处理器的新一般方法通过允许在可重配置逻辑中实现更强大，紧密耦合的指令集扩展来实现应用中的更高性能。 可以通过自动和半自动方法发现和设计新的指令集配置。 改进的可重配置执行单元支持深度流水线，添加附加寄存器和寄存器文件，具有许多源和目标寄存器的复合指令以及宽数据路径。 新的接口方法允许混合处理器和其他逻辑之间的较低延迟，更高带宽连接。

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