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    LAYOUT STRUCTURE OF BIT LINE SENSE AMPLIFIERS FOR A SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    LAYOUT STRUCTURE OF BIT LINE SENSE AMPLIFIERS FOR A SEMICONDUCTOR MEMORY DEVICE 有权
    用于半导体存储器件的位线感测放大器的布局结构

    公开(公告)号：US20110103166A1

    公开(公告)日：2011-05-05

    申请号：US12987539

    申请日：2011-01-10

    Applicant: YOUNG-SUN MIN ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    Inventor： YOUNG-SUN MIN ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    IPC: G11C7/06 ,  H03F3/68 ,  H03F3/16 ,  G06F17/50

    CPC classification number: G11C7/18 ,  G11C5/025 ,  G11C7/065 ,  G11C2207/002

    Abstract: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

    Abstract translation: 用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。 在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

    Layout structure of bit line sense amplifiers for a semiconductor memory device
    4.
    发明授权
    Layout structure of bit line sense amplifiers for a semiconductor memory device 有权
    用于半导体存储器件的位线读出放大器的布局结构

    公开(公告)号：US07869239B2

    公开(公告)日：2011-01-11

    申请号：US12078724

    申请日：2008-04-03

    Applicant: Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    Inventor： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    IPC: G11C5/02

    CPC classification number: G11C7/18 ,  G11C5/025 ,  G11C7/065 ,  G11C2207/002

    Abstract: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

    Abstract translation: 用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。 在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

    Integrated circuit memories including fuses between a decoder and a memory array for disabling defective storage cells in the memory array
    5.
    发明授权
    Integrated circuit memories including fuses between a decoder and a memory array for disabling defective storage cells in the memory array 失效
    集成电路存储器，包括解码器和用于禁止存储器阵列中的有缺陷的存储单元的存储器阵列之间的熔丝

    公开(公告)号：US06215715B1

    公开(公告)日：2001-04-10

    申请号：US09346567

    申请日：1999-07-01

    Applicant: Kyu-chan Lee ,  Chul-woo Yi

    Inventor： Kyu-chan Lee ,  Chul-woo Yi

    IPC: G11C800

    CPC classification number: G11C29/785

    Abstract: An integrated circuit memory device includes a two-dimensional memory array in which the first and second dimensions extend in first and second directions respectively. The memory device further includes a decoder for the first dimension and a plurality of fuses between the decoder and the memory array. Upon encountering a defective storage cell in the memory array, the appropriate fuse can be cut to physically segregate the decoder from the defective cell. This allows the memory to operate without any delay inserted for switching to a spare or redundant memory array of storage cells, thus maximizing the memory operating speed. In a preferred embodiment, the fuses are arranged such that the relative spacing between the fuses proceeds substantially along the second direction and the fuses are oriented lengthwise in the first direction. By following this arrangement, the impact on the layout area for the memory device is minimal.

    Abstract translation: 集成电路存储器件包括二维存储器阵列，其中第一和第二尺寸分别在第一和第二方向上延伸。 存储器件还包括用于第一维度的解码器和解码器与存储器阵列之间的多个熔丝。 当遇到存储器阵列中的有缺陷的存储单元时，可以切割适当的熔丝以使解码器与有缺陷的单元物理隔离。 这允许存储器在没有任何延迟的情况下操作以切换到存储单元的备用或冗余存储器阵列，从而最大化存储器操作速度。 在优选实施例中，保险丝被布置成使得熔丝之间的相对间隔基本上沿着第二方向进行，并且熔丝在第一方向上纵向定向。 通过遵循这种布置，对存储器件的布局区域的影响是最小的。

    Semiconductor memory device
    6.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20080298111A1

    公开(公告)日：2008-12-04

    申请号：US12079995

    申请日：2008-03-31

    Applicant: Hyo-Joo Ahn ,  Kyu-Chan Lee ,  Chul-Woo Yi

    Inventor： Hyo-Joo Ahn ,  Kyu-Chan Lee ,  Chul-Woo Yi

    IPC: G11C5/02 ,  G11C7/00

    CPC classification number: G11C5/025 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/11898

    Abstract: A semiconductor memory device includes: a substrate with first and second memory-cell array regions disposed on first and second substrate sides and first and second sense-circuit regions disposed on the first and second substrate sides between the first and second memory-cell array regions; first and second bitlines coupled to a plurality of memory cells in the first memory-cell array region; first and second complementary bitlines coupled to a plurality of memory cells in the second memory-cell array region; first and second column-selection transistors formed in the first sense-circuit region, and selectively couple the first bitline and the first complementary bitline to a first input/output (I/O) line and a first complementary I/O line; and third and fourth column-selection transistors formed in the second sense-circuit region, and selectively couple the second bitline and the second complementary bitline to a second I/O line and a second complementary I/O line.

    Abstract translation: 半导体存储器件包括：具有设置在第一和第二衬底侧上的第一和第二存储单元阵列区域的衬底以及设置在第一和第二衬底侧的第一和第二存储单元阵列区域之间的第一和第二感测电路区域 ; 第一和第二位线耦合到第一存储单元阵列区域中的多个存储单元; 第一和第二互补位线耦合到第二存储单元阵列区域中的多个存储单元; 形成在第一感测电路区域中的第一和第二列选择晶体管，并且将第一位线和第一互补位线选择性地耦合到第一输入/输出（I / O）线和第一互补I / O线; 以及形成在第二感测电路区域中的第三和第四列选择晶体管，并且选择性地将第二位线和第二互补位线耦合到第二I / O线和第二互补I / O线。

    Semiconductor memory device having an open bit line structure, and method of testing the same
    7.
    发明授权
    Semiconductor memory device having an open bit line structure, and method of testing the same 有权
    具有开放位线结构的半导体存储器件及其测试方法

    公开(公告)号：US07447088B2

    公开(公告)日：2008-11-04

    申请号：US11625606

    申请日：2007-01-22

    Applicant: Chul-Woo Yi

    Inventor： Chul-Woo Yi

    IPC: G11C7/00

    CPC classification number: G11C29/24 ,  G11C5/063 ,  G11C7/14 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4097 ,  G11C11/4099 ,  G11C2029/1204

    Abstract: A memory core having an open bit line structure and a semiconductor memory device having the memory core includes an edge sub-array and a dummy bit line control circuit. The edge sub-array has a plurality of word lines, a plurality of bit lines and a plurality of dummy bit lines. The dummy bit line control circuit amplifies and latches voltage signals of the dummy bit lines in a test sensing mode. Accordingly, the semiconductor memory device having the memory core may test defects of the edge sub-array included in the memory core.

    Abstract translation: 具有开放位线结构的存储器芯和具有存储器芯的半导体存储器件包括边缘子阵列和虚拟位线控制电路。 边缘子阵列具有多个字线，多个位线和多个虚拟位线。 虚拟位线控制电路在测试感测模式下放大并锁存虚拟位线的电压信号。 因此，具有存储器核心的半导体存储器件可以测试存储器芯中包括的边缘子阵列的缺陷。

    Layout structure of bit line sense amplifiers for a semiconductor memory device
    8.
    发明申请
    Layout structure of bit line sense amplifiers for a semiconductor memory device 有权
    用于半导体存储器件的位线读出放大器的布局结构

    公开(公告)号：US20080259668A1

    公开(公告)日：2008-10-23

    申请号：US12078724

    申请日：2008-04-03

    Applicant: Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    Inventor： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    IPC: G11C5/02 ,  G11C7/06

    CPC classification number: G11C7/18 ,  G11C5/025 ,  G11C7/065 ,  G11C2207/002

    Abstract: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

    Abstract translation: 用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。 在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

    Internal boosted voltage generator of semiconductor memory device
    9.
    发明授权
    Internal boosted voltage generator of semiconductor memory device 失效
    半导体存储器件的内部升压电压发生器

    公开(公告)号：US5901055A

    公开(公告)日：1999-05-04

    申请号：US915220

    申请日：1997-08-20

    Applicant: Chul-woo Yi ,  Hoon Choi

    Inventor： Chul-woo Yi ,  Hoon Choi

    IPC: G11C11/413 ,  G11C5/14 ,  G11C11/407 ,  H02M3/07 ,  H02M3/18

    CPC classification number: G11C5/145 ,  H02M3/07

    Abstract: An internal boosted voltage generator for a semiconductor memory device eliminates excessive increases in boosted voltage and reduces current consumption even though the power supply voltage increases. The internal boosted voltage generator includes a pumping portion for pumping a signal from an output node in response to a control signal, a precharging portion for precharging the output node of the pumping portion, and a controlling portion interposed between the pumping portion and the precharge portion. The controlling portion is a pulse generator that varies the precharge time of the precharging portion by varying the pulse with of an output signal according to the power supply voltage. The output signal of the controlling portion has a relatively narrow pulse width at high power supply voltages and a wider pulse width at low power supply voltages. Therefore, the device is not exposed to excessive stress even though the power supply voltage increases greatly.

    Abstract translation: 用于半导体存储器件的内部升压电压发生器消除了升压电压的过度增加，并且即使电源电压增加也降低了电流消耗。 内部升压电压发生器包括用于响应于控制信号从输出节点泵浦信号的泵送部分，用于对泵送部分的输出节点进行预充电的预充电部分和插入在泵送部分和预充电部分之间的控制部分 。 控制部分是通过根据电源电压改变输出信号的脉冲来改变预充电部分的预充电时间的脉冲发生器。 控制部分的输出信号在高电源电压下具有相对窄的脉冲宽度，在低电源电压下具有较宽的脉冲宽度。 因此，即使电源电压大大增加，器件也不会暴露于过度的应力。

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