公开(公告)号：US20130063175A1

公开(公告)日：2013-03-14

申请号：US13231812

申请日：2011-09-13

Applicant: Bi-Ling Lin ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Lee-Der Chen ,  Jiaw-Ren Shih ,  Chwei-Ching Chiu

Inventor： Bi-Ling Lin ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Lee-Der Chen ,  Jiaw-Ren Shih ,  Chwei-Ching Chiu

IPC: G01R31/26 ,  H01L23/538 ,  H01L23/522

CPC classification number: H01L23/5256 ,  G01R31/2853 ,  G01R31/2858 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.

Abstract translation: 公开了半导体器件组件和方法。 在一个实施例中，半导体器件部件包括具有第一表面，与第一表面相对的第二表面，第一端和与第一端相对的第二端的导电段。 第一通孔在第一端耦合到导电段的第二表面。 第二通孔在第二端处耦合到导电段的第一表面，并且第三通孔在第二端耦合到导电段的第二表面。

公开(公告)号：US6127833A

公开(公告)日：2000-10-03

申请号：US225382

申请日：1999-01-04

Applicant: Wen-Teng Wu ,  Chwei-Ching Chiu ,  Chi-Min Hsieh

Inventor： Wen-Teng Wu ,  Chwei-Ching Chiu ,  Chi-Min Hsieh

IPC: G01R31/28 ,  G01R31/02 ,  G01R31/26

CPC classification number: G01R31/2886 ,  H01L2224/73265

Abstract: A method for forming a semiconductor test carrier including an insulating substrate having a top surface, a bottom surface, periphery; with a rectangular cavity centrally located on the top surface and extending through to the bottom surface. A conductive ground trace formed on the top surface at the periphery of the cavity with conductive corner power traces formed adjacent each corner of the ground trace, with a ruled pattern of conductive wire bond pads encircling the corner power traces. Wire bond pads are formed in a linear array on each of the four sides encircling the power traces. A first interstitial ball pad array encircles the conductive wire bond pads and connects with the bottom surface by way of conductive vias communicating with a second interstitial ball pad array at the bottom surface. A glass plate is attached to the underside of the insulated substrate to form a bottom supporting surface in the rectangular cavity. A semiconductor device is placed in the cavity and its backside adhesively bonded to the glass plate. The appropriate input/output terminals of the device are connected to appropriate wire bond pads and traces on the top surface of the substrate with metallurgically bonded conductive wire. The exposed ends of the wires are encapsulated with a sealing polymer.

Abstract translation: 一种用于形成半导体测试载体的方法，所述半导体测试载体包括具有顶表面，底表面，外围的绝缘基底; 中心位于顶表面上并延伸到底表面的矩形腔。 形成在腔的周边的顶表面上的导电接地迹线，其具有形成在接地迹线的每个角附近的导电拐角电力迹线，其具有围绕拐角功率迹线的导线接合焊盘的刻划图案。 引线接合焊盘在围绕电源迹线的四个侧面中的每一个上以线性阵列形成。 第一间隙球垫阵列环绕导电接合焊盘并且通过与底表面处的第二间隙球垫阵列连通的导电通孔与底表面连接。 玻璃板连接到绝缘基板的下侧，以在矩形空腔中形成底部支撑表面。 半导体器件放置在空腔中，其背面粘合到玻璃板上。 器件的适当的输入/输出端子使用冶金结合的导线连接到衬底顶表面上的适当引线接合焊盘和迹线。 电线的露出端用密封聚合物包封。

公开(公告)号：US08648592B2

公开(公告)日：2014-02-11

申请号：US13231812

申请日：2011-09-13

Applicant: Bi-Ling Lin ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Lee-Der Chen ,  Jiaw-Ren Shih ,  Chwei-Ching Chiu

Inventor： Bi-Ling Lin ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Lee-Der Chen ,  Jiaw-Ren Shih ,  Chwei-Ching Chiu

IPC: G01V3/00

CPC classification number: H01L23/5256 ,  G01R31/2853 ,  G01R31/2858 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.

Abstract translation: 公开了半导体器件组件和方法。 在一个实施例中，半导体器件部件包括具有第一表面，与第一表面相对的第二表面，第一端和与第一端相对的第二端的导电段。 第一通孔在第一端耦合到导电段的第二表面。 第二通孔在第二端处耦合到导电段的第一表面，并且第三通孔在第二端耦合到导电段的第二表面。