中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.015 seconds)

    Integrated MOS one-way isolation coupler and a semiconductor chip having an integrated MOS isolation one-way coupler located thereon
    1.
    发明授权
    Integrated MOS one-way isolation coupler and a semiconductor chip having an integrated MOS isolation one-way coupler located thereon 有权
    集成MOS单向隔离耦合器和位于其上的集成MOS隔离单向耦合器的半导体芯片

    公开(公告)号：US07319261B1

    公开(公告)日：2008-01-15

    申请号：US10721039

    申请日：2003-11-21

    Applicant: James Anthony Power ,  Michael Anthony O'Neill ,  Colin Gerard Lyden

    Inventor： James Anthony Power ,  Michael Anthony O'Neill ,  Colin Gerard Lyden

    IPC: H01L29/82

    CPC classification number: H01L27/22 ,  H01L23/5227 ,  H01L27/0617 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A MOS isolation coupler is formed on a semiconductor chip by a CMOS process and comprises an inductor coil for generating a magnetic field in response to an input signal applied to terminals thereof. A MAGFET having a split drain formed by respective drain portions is formed on the semiconductor chip below the inductor coil, so that a current difference is induced between the drain currents in the drain portions which is proportional to the strength of the magnetic field generated by the inductor coil resulting from the input signal. The MAGFET is formed prior to the inductor coil. An oxide isolating layer is provided over the MAGFET, and the inductor coil is formed on the oxide layer. The depth of the oxide layer is sufficient for providing the desired amount of electrical isolation, while at the same time locating the inductor coil sufficiently close to the MAGFET so that the magnetic field generated by the inductor coil, extending axially through the inductor coil cuts the channel of the MAGFET substantially perpendicularly.

    Abstract translation: MOS隔离耦合器通过CMOS工艺在半导体芯片上形成，并且包括用于响应于施加到其端子的输入信号而产生磁场的电感线圈。 在电感线圈下方的半导体芯片上形成具有由相应的漏极部分形成的分离漏极的MAGFET，从而在漏极部分中的漏极电流之间产生电流差异，该漏极电流与由 由输入信号产生的电感线圈。 在电感线圈之前形成MAGFET。 在MAGFET上设置氧化物隔离层，在氧化物层上形成电感线圈。 氧化物层的深度足以提供所需量的电隔离，同时将电感线圈定位成足够靠近MAGFET，使得由电感线圈产生的磁场沿轴向延伸穿过电感线圈切断 MAGFET的通道基本垂直。

    Analog to digital converter with dither
    2.
    发明授权
    Analog to digital converter with dither 有权
    具有抖动的模数转换器

    公开(公告)号：US07286075B2

    公开(公告)日：2007-10-23

    申请号：US11273196

    申请日：2005-11-14

    Applicant: Michael Hennessy ,  Christopher Peter Hurrell ,  Colin Gerard Lyden

    Inventor： Michael Hennessy ,  Christopher Peter Hurrell ,  Colin Gerard Lyden

    IPC: H03M1/12

    CPC classification number: H03M1/0639 ,  H03M1/468

    Abstract: An analog to digital converter is provided comprising an array of capacitors for sampling an input, each capacitor having at least one associated switch for controllably connecting a terminal of the capacitor to a first reference voltage or to a second reference voltage; and a sequence generator for generating a sequence of bits, wherein during sampling of the input onto the array of capacitors an output of the sequence generator is supplied to the switches of a first group of capacitors to control whether a given capacitor within the first group is connected by its associated switch to the first reference voltage or to the second reference voltage.

    Abstract translation: 提供了一种模数转换器，包括用于对输入进行采样的电容器阵列，每个电容器具有至少一个相关联的开关，用于将电容器的端子可控地连接到第一参考电压或第二参考电压; 以及用于产生位序列的序列发生器，其中在对所述电容器阵列的输入进行采样期间，所述序列发生器的输出被提供给第一组电容器的开关，以控制所述第一组内的给定电容器是否为 通过其相关联的开关连接到第一参考电压或第二参考电压。

    Method for one-way coupling an input signal to an integrated circuit
    3.
    发明授权
    Method for one-way coupling an input signal to an integrated circuit 有权
    将输入信号单向耦合到集成电路的方法

    公开(公告)号：US07419838B2

    公开(公告)日：2008-09-02

    申请号：US11985541

    申请日：2007-11-15

    Applicant: James Anthony Power ,  Michael Anthony O'Neill ,  Colin Gerard Lyden

    Inventor： James Anthony Power ,  Michael Anthony O'Neill ,  Colin Gerard Lyden

    IPC: H01L21/00

    CPC classification number: H01L27/22 ,  H01L23/5227 ,  H01L27/0617 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for one-way coupling an input signal to an integrated circuit on a semiconductor chip with the integrated circuit electrically isolated from the input signal comprises forming a MOS isolation coupler on the semiconductor chip by a CMOS process. The MOS isolation coupler comprises an inductor coil for generating a magnetic field in response to an input signal applied to terminals thereof. A MAGFET having a split drain formed by respective drain portions is formed on the semiconductor chip below the inductor coil, so that a current difference is induced between the drain currents in the drain portions which is proportional to the strength of the magnetic field generated by the inductor coil resulting from the input signal. The MAGFET is formed prior to the inductor coil. An oxide isolating layer is provided over the MAGFET, and the inductor coil is formed on the oxide layer. The depth of the oxide layer is sufficient for providing the desired amount of electrical isolation, while at the same time locating the inductor coil sufficiently close to the MAGFET so that the magnetic field generated by the inductor coil, extending axially through the inductor coil cuts the channel of the MAGFET substantially perpendicularly.

    Abstract translation: 将输入信号单向耦合到具有与输入信号电隔离的集成电路的半导体芯片上的集成电路的方法包括通过CMOS工艺在半导体芯片上形成MOS隔离耦合器。 MOS隔离耦合器包括用于响应于施加到其端子的输入信号而产生磁场的电感线圈。 在电感线圈下方的半导体芯片上形成具有由相应的漏极部分形成的分离漏极的MAGFET，从而在漏极部分中的漏极电流之间产生电流差异，该漏极电流与由 由输入信号产生的电感线圈。 在电感线圈之前形成MAGFET。 在MAGFET上设置氧化物隔离层，在氧化物层上形成电感线圈。 氧化物层的深度足以提供所需量的电隔离，同时将电感线圈定位成足够靠近MAGFET，使得由电感线圈产生的磁场沿轴向延伸穿过电感线圈切断 MAGFET的通道基本垂直。

    INL curve correction in a pipeline ADC
    4.
    发明授权
    INL curve correction in a pipeline ADC 有权
    管线ADC中的INL曲线校正

    公开(公告)号：US07348906B2

    公开(公告)日：2008-03-25

    申请号：US11224432

    申请日：2005-09-12

    Applicant: John J. O'Donnell ,  Colin Gerard Lyden ,  David G. Nairn

    Inventor： John J. O'Donnell ,  Colin Gerard Lyden ,  David G. Nairn

    IPC: H03M1/20

    CPC classification number: H03M1/0641 ,  H03M1/069 ,  H03M1/167 ,  H03M3/424

    Abstract: The present invention relates to a method and system for reducing integral non linearity errors in a pipeline Analog to Digital Converter (ADC). The invention provides in a first embodiment a method comprising the steps of: adding an analog dither signal to the analog input signal of a pipeline Analog to Digital Converter, and converting the analog input signal to a digital output signal by means of the pipeline Analog to Digital Converter. The amplitude of the analog dither signal is determined by the architecture of the Analog to Digital Converter. The invention also provides in a second embodiment a circuit comprising a pipeline analog to digital converter for converting an analog input signal to a digital output signal and a feedback circuit coupled to the converter such that the digital output signal is adapted to have an average non linearity error value of about zero LSBs.

    Abstract translation: 本发明涉及用于减少管线模数转换器（ADC）中的积分非线性误差的方法和系统。 本发明在第一实施例中提供了一种方法，包括以下步骤：将模拟抖动信号添加到流水线模数转换器的模拟输入信号，并通过管线将模拟输入信号转换为数字输出信号模拟到 数字转换器 模拟抖动信号的幅度由模数转换器的架构决定。 本发明还在第二实施例中提供一种包括用于将模拟输入信号转换为数字输出信号的流水线模数转换器和耦合到转换器的反馈电路的电路，使得数字输出信号适于具有平均非线性度 误差值约零LSB。

    Analog to digital converter
    10.
    发明授权
    Analog to digital converter 有权
    模数转换器

    公开(公告)号：US07274321B2

    公开(公告)日：2007-09-25

    申请号：US11273220

    申请日：2005-11-14

    Applicant: Christopher Peter Hurrell ,  Colin Gerard Lyden

    Inventor： Christopher Peter Hurrell ,  Colin Gerard Lyden

    IPC: H03M1/12

    CPC classification number: H03M1/145 ,  H03M1/144 ,  H03M1/468

    Abstract: A analog to digital converter, comprising: an input for receiving an input signal to be digitized; a first converter core for performing a first part of an analog to digital conversion, and for outputting a first digital result; a first residue calculator for calculating a first residue as a difference between the input signal and the first digital result; a second converter core for performing a second part of the analog to digital conversion by converting the first residue; wherein at least one of the first and second converter cores comprises at least three analog to digital conversion engines and a controller for controlling the operation of the engines such that the engines collaborate to perform a successive approximation search, and wherein a plurality of bits can be determined during a single trial step of the successive approximation search.

    Abstract translation: 一种模数转换器，包括：用于接收要被数字化的输入信号的输入; 用于执行模数转换的第一部分并用于输出第一数字结果的第一转换器核心; 第一残差计算器，用于计算第一残差作为输入信号和第一数字结果之间的差; 第二转换器核，用于通过转换第一残差来执行模数转换的第二部分; 其中所述第一和第二转换器核心中的至少一个包括至少三个模数转换引擎和用于控制引擎的操作的控制器，使得引擎协同执行逐次逼近搜索，并且其中多个位可以是 在逐次逼近搜索的单个试验步骤中确定。

Patent Agency Ranking