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    Direct digital synthesizer for reference frequency generation
    1.
    发明申请
    Direct digital synthesizer for reference frequency generation 有权
    直接数字合成器，用于参考频率发生

    公开(公告)号：US20100052797A1

    公开(公告)日：2010-03-04

    申请号：US12229948

    申请日：2008-08-28

    Applicant: L. Richard Carley ,  Anthony L. Tsangaropoulos ,  Esa Tarvainen

    Inventor： L. Richard Carley ,  Anthony L. Tsangaropoulos ,  Esa Tarvainen

    IPC: H03L7/00

    CPC classification number: H03L7/0814 ,  G06F1/025

    Abstract: A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fosc and outputs some integer fraction of those pulses at an instantaneous frequency fVp that is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P(1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to receiving an overflow signal. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator that further controls the frequency of the multi-modulus divider output signal (Vp) to provide an output signal (VD) with an fOUT that has improved phase and timing jitter performance over prior art direct digital frequency synthesizer architectures.

    Abstract translation: 具有多模式分频器，数控振荡器和可编程延迟发生器的直接数字频率合成器。 多模式分频器接收具有输入脉冲频率fosc的输入时钟，并且以输入频率的某个整数分数（1 / P）的瞬时频率fVp输出那些脉冲的一些整数。 响应于来自数控振荡器的信号，多模式分配器在至少两个P（1 / P或1 / P + 1）之间选择。 数字振荡器接收一个值，该值是在溢出发生之前所需的累加器增量（即，分割的脉冲边沿数），这导致多模式分频器响应于接收到溢出信号而改变分频比。 数字振荡器还将溢出信号和延迟信号输出到延迟发生器，该延迟发生器进一步控制多模式分频器输出信号（Vp）的频率以向具有改进的相位的fOUT提供输出信号（VD），并且 相比现有技术的直接数字频率合成器架构的定时抖动性能。

    DC monitor for active device speed
    3.
    发明授权
    DC monitor for active device speed 失效
    DC监视器用于有效的设备速度

    公开(公告)号：US5870352A

    公开(公告)日：1999-02-09

    申请号：US893639

    申请日：1997-07-11

    Applicant: Esa Tarvainen ,  Hannu Roukainen

    Inventor： Esa Tarvainen ,  Hannu Roukainen

    IPC: G01R35/00 ,  H01L23/544 ,  H04B17/00 ,  G04F8/00 ,  G01R15/12 ,  H01L21/60

    CPC classification number: G01R35/00 ,  H01L22/34 ,  H01L2924/0002

    Abstract: Methods and circuits to measure the speed of silicon test structures using direct current test equipment. Each test structure comprises an oscillator and a detector. Oscillations started by a direct current input signal are rectified by the detector into a direct current output signal. Start of oscillations cause a jump in the output signal and that point is correlated with the input signal strength which in turn is correlated to the speed of the test circuits. By knowing the speed of the test circuits the quality of the manufacturing process can be checked. Direct current greatly simplifies measurement so that 100% testing can be performed.

    Abstract translation: 使用直流测试设备测量硅测试结构速度的方法和电路。 每个测试结构包括振荡器和检测器。 由直流输入信号开始的振荡由检波器整流为直流输出信号。 振荡开始导致输出信号的跳跃，该点与输入信号强度相关，输入信号强度又与测试电路的速度相关。 通过了解测试电路的速度，可以检查制造过程的质量。 直流电极大大简化了测量，可以进行100％的测试。

    Direct digital synthesizer for reference frequency generation
    6.
    发明授权
    Direct digital synthesizer for reference frequency generation 有权
    直接数字合成器，用于参考频率发生

    公开(公告)号：US07724097B2

    公开(公告)日：2010-05-25

    申请号：US12229948

    申请日：2008-08-28

    Applicant: L. Richard Carley ,  Anthony L. Tsangaropoulos ,  Esa Tarvainen

    Inventor： L. Richard Carley ,  Anthony L. Tsangaropoulos ,  Esa Tarvainen

    IPC: H03B1/00 ,  H03K21/00 ,  H03K21/08 ,  H03K21/38

    CPC classification number: H03L7/0814 ,  G06F1/025

    Abstract: A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fosc and outputs some integer fraction of those pulses at an instantaneous frequency fVp that is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to receiving an overflow signal. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator that further controls the frequency of the multi-modulus divider output signal (Vp) to provide an output signal (VD) with an fout that has improved phase and timing jitter performance over prior art direct digital frequency synthesizer architectures.

    Abstract translation: 具有多模式分频器，数控振荡器和可编程延迟发生器的直接数字频率合成器。 多模式分频器接收具有输入脉冲频率fosc的输入时钟，并且以输入频率的某个整数分数（1 / P）的瞬时频率fVp输出那些脉冲的一些整数。 响应于来自数控振荡器的信号，多模式分配器在至少两个P（1 / P或1 / P + 1）之间选择。 数字振荡器接收一个值，该值是在溢出发生之前所需的累加器增量（即，分割的脉冲边沿数），这导致多模式分频器响应于接收到溢出信号而改变分频比。 数字振荡器还将溢出信号和延迟信号输出到延迟发生器，该延迟发生器进一步控制多模式分频器输出信号（Vp）的频率，以提供具有改进相位的fout的输出信号（VD），并且 相比现有技术的直接数字频率合成器架构的定时抖动性能。

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