公开(公告)号：US20130056837A1

公开(公告)日：2013-03-07

申请号：US13244365

申请日：2011-09-24

Applicant: Jin-Aun Ng ,  Maxi Chang ,  Jen-Sheng Yang ,  Ta-Wei Lin ,  Shih-Hao Lo ,  Chih-Yang Yeh ,  Hui-Wen Lin ,  Jung-Hui Kao ,  Yuan-Tien Tu ,  Huan-Just Lin ,  Chih-Tang Peng ,  Pei-Ren Jeng ,  Bao-Ru Young ,  Hak-Lay Chuang

Inventor： Jin-Aun Ng ,  Maxi Chang ,  Jen-Sheng Yang ,  Ta-Wei Lin ,  Shih-Hao Lo ,  Chih-Yang Yeh ,  Hui-Wen Lin ,  Jung-Hui Kao ,  Yuan-Tien Tu ,  Huan-Just Lin ,  Chih-Tang Peng ,  Pei-Ren Jeng ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC: H01L29/772 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L21/28229 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.

Abstract translation: 制造集成电路的方法包括提供半导体衬底并在诸如高k电介质的衬底上形成栅极电介质。 在半导体衬底上形成金属栅极结构，并在其上形成一个薄的电介质膜。 薄介电膜包括从金属栅极与金属组合的氮氧化合物。 该方法还包括在金属栅极结构的两侧提供层间电介质（ILD）。

公开(公告)号：US08222136B2

公开(公告)日：2012-07-17

申请号：US12906868

申请日：2010-10-18

Applicant: Yuan-Tien Tu ,  Tsai-Chun Li ,  Huan-Just Lin ,  Shih-Chang Chen

Inventor： Yuan-Tien Tu ,  Tsai-Chun Li ,  Huan-Just Lin ,  Shih-Chang Chen

IPC: H01L21/4763

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/76816

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成层。 所述方法包括在所述层中形成暴露所述衬底的第一区域的第一开口。 该方法包括通过第一溅射工艺去除在第一区域上形成的第一氧化层。 该方法包括用导电材料填充第一开口。 所述方法包括在所述层中形成暴露所述衬底的第二区域的第二开口，所述第二区域不同于所述第一区域。 该方法包括通过第二溅射工艺除去在第二区域上形成的第二氧化层。 第一和第二溅射工艺之一比另一个更强大。

公开(公告)号：US08129279B2

公开(公告)日：2012-03-06

申请号：US12250239

申请日：2008-10-13

Applicant: Shen-Nan Lee ,  Ying-Mei Lin ,  Yu-Jen Cheng ,  Keung Hui ,  Huan-Just Lin

Inventor： Shen-Nan Lee ,  Ying-Mei Lin ,  Yu-Jen Cheng ,  Keung Hui ,  Huan-Just Lin

IPC: H01L21/302

CPC classification number: B24B37/013 ,  B24B49/12

Abstract: A method of performing chemical mechanical polish (CMP) processes on a wafer includes providing the wafer; determining a thickness profile of a feature on a surface of the wafer; and, after the step of determining the thickness profile, performing a high-rate CMP process on the feature using a polish recipe to substantially achieve a within-wafer thickness uniformity of the feature. The polish recipe is determined based on the thickness profile.

Abstract translation: 在晶片上进行化学机械抛光（CMP）工艺的方法包括提供晶片; 确定晶片表面上的特征的厚度分布; 并且在确定厚度分布的步骤之后，使用抛光配方对特征进行高速率CMP处理，以基本上实现特征的晶片内厚度均匀性。 根据厚度分布确定抛光配方。

公开(公告)号：US07157350B2

公开(公告)日：2007-01-02

申请号：US10847607

申请日：2004-05-17

Applicant: Ji-Yi Yang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Huan-Just Lin

Inventor： Ji-Yi Yang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Huan-Just Lin

IPC: H01L21/76

CPC classification number: H01L21/3247 ,  H01L21/76232 ,  H01L21/76283 ,  H01L27/1203

Abstract: Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

公开(公告)号：US07023042B2

公开(公告)日：2006-04-04

申请号：US10755498

申请日：2004-01-12

Applicant: Bor-Wen Chan ,  Huan-Just Lin ,  Hun-Jan Tao

Inventor： Bor-Wen Chan ,  Huan-Just Lin ,  Hun-Jan Tao

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L28/88 ,  H01L27/10814 ,  H01L27/10852

Abstract: A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysificon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increased surface area as a result of the formation of the lateral grooves.

Abstract translation: 已经开发了用于形成具有增加的表面积的DRAM叠层电容器结构的工艺。 该工艺在用于限定存储节点结构的干蚀刻过程中，在多晶硅存储节点结构的侧面形成横向凹槽。 这些凹槽是选择性地和侧向地形成在离子植入的静脉中，这些静脉又通过一系列离子注入步骤而被放置在本征多晶硅层中的各种深度处，每个离子注入步骤以特定的注入能量进行。 存储节点结构的同位素组分定义了干蚀刻过程，选择性地以高于离子植入的静脉之间的聚合物的非离子注入区域的速率以更高的速率蚀刻高度掺杂的离子植入的静脉，产生颈缩轮廓， 存储节点结构，由于形成横向槽而具有增加的表面积。

公开(公告)号：US20050253194A1

公开(公告)日：2005-11-17

申请号：US10847607

申请日：2004-05-17

Applicant: Ji-Yi Yang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Huan-Just Lin

Inventor： Ji-Yi Yang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Huan-Just Lin

IPC: H01L21/324 ,  H01L21/762 ,  H01L27/01 ,  H01L27/12

CPC classification number: H01L21/3247 ,  H01L21/76232 ,  H01L21/76283 ,  H01L27/1203

Abstract: Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

Abstract translation: 通过退火将体硅转变成SOI样结构。 沟槽形成在大量衬底中以限定器件位置。 沟槽的下部在氢气气氛中在低压下退火。 这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。 相邻的空洞每个居住在中间位置的一半左右。 消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

公开(公告)号：US06235440B1

公开(公告)日：2001-05-22

申请号：US09434563

申请日：1999-11-12

Applicant: Hun-Jan Tao ,  Huan-Just Lin ,  Fang-Cheng Chen

Inventor： Hun-Jan Tao ,  Huan-Just Lin ,  Fang-Cheng Chen

IPC: G03F900

CPC classification number: G03F7/70625 ,  G03F7/40 ,  H01L22/20 ,  Y10S438/949

Abstract: The invention is a process for reducing variations in CD from wafer to wafer. It begins by increasing all line widths in the original pattern data file by a fixed amount that is sufficient to ensure that all lines will be wider than the lowest acceptable CD value. Using a reticle generated from this modified data file, the pattern is formed in photoresist and the resulting CD value is determined. If this turns out be outside (above) the acceptable CD range, the amount of deviation from the ideal CD value is determined and fed into suitable software that calculates the control parameters (usually time) for an ashing routine. After ashing, the lines will have been reduced in width by the amount necessary to obtain the correct CD. A fringe benefit of this trimming process is that edge roughness of the photoresist lines is reduced and line feet are removed.

Abstract translation: 本发明是减少CD从晶片到晶片的变化的方法。 它首先将原始图案数据文件中的所有行宽增加一个固定的量，这足以确保所有行都比最低可接受的CD值宽。 使用由该修改的数据文件生成的掩模版，在光致抗蚀剂中形成图案，并确定所得到的CD值。 如果事实证明在可接受的CD范围之外（以上），则确定与理想CD值的偏差量，并将其馈送到计算灰化程序的控制参数（通常为时间）的合适软件中。 灰化后，线条的宽度减小了获得正确CD所需的量。 这种修整过程的附带优点是减少了光致抗蚀剂线的边缘粗糙度并且去除了线脚。

公开(公告)号：US08673736B2

公开(公告)日：2014-03-18

申请号：US11546768

申请日：2006-10-12

Applicant: Ji-Yi Yang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Huan-Just Lin

Inventor： Ji-Yi Yang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Huan-Just Lin

IPC: H01L21/762

CPC classification number: H01L21/3247 ,  H01L21/76232 ,  H01L21/76283 ,  H01L27/1203

Abstract: Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

Abstract translation: 通过退火将体硅转变成SOI样结构。 沟槽形成在大量衬底中以限定器件位置。 沟槽的下部在氢气气氛中在低压下退火。 这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。 相邻的空洞每个居住在中间位置的一半左右。 消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

公开(公告)号：US08546227B2

公开(公告)日：2013-10-01

申请号：US13289112

申请日：2011-11-04

Applicant: Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

Inventor： Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

IPC: H01L21/336 ,  H01L21/44

CPC classification number: H01L29/78 ,  H01L21/28114 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/823842 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making an integrated circuit includes providing a substrate with a high-k dielectric and providing a polysilicon gate structure over the high-k dielectric. A doping process is performed on the substrate adjacent to the polysilicon gate structure, after which the polysilicon gate structure is removed and replaced with a metal gate structure. An interlayer dielectric (ILD) is deposited over the metal gate structure and the doped substrate, and a dry etch process forms a trench in the ILD to a top surface of the metal gate structure. After the dry etch process, a wet etch process forms an undercut near the top surface of the metal gate structure. The trench and undercut are then filled with a conductive material.

Abstract translation: 制造集成电路的方法包括：提供具有高k电介质的衬底并在高k电介质上提供多晶硅栅极结构。 在与多晶硅栅极结构相邻的衬底上执行掺杂工艺，之后去除多晶硅栅极结构并用金属栅极结构代替。 在金属栅极结构和掺杂衬底上沉积层间电介质（ILD），并且干蚀刻工艺在ILD中形成到金属栅极结构的顶表面的沟槽。 在干蚀刻工艺之后，湿蚀刻工艺在金属栅极结构的顶表面附近形成底切。 然后用导电材料填充沟槽和底切。

公开(公告)号：US20130069174A1

公开(公告)日：2013-03-21

申请号：US13289112

申请日：2011-11-04

Applicant: Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

Inventor： Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L21/28114 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/823842 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making an integrated circuit includes providing a substrate with a high-k dielectric and providing a polysilicon gate structure over the high-k dielectric. A doping process is performed on the substrate adjacent to the polysilicon gate structure, after which the polysilicon gate structure is removed and replaced with a metal gate structure. An interlayer dielectric (ILD) is deposited over the metal gate structure and the doped substrate, and a dry etch process forms a trench in the ILD to a top surface of the metal gate structure. After the dry etch process, a wet etch process forms an undercut near the top surface of the metal gate structure. The trench and undercut are then filled with a conductive material.

Abstract translation: 制造集成电路的方法包括：提供具有高k电介质的衬底并在高k电介质上提供多晶硅栅极结构。 在与多晶硅栅极结构相邻的衬底上执行掺杂工艺，之后去除多晶硅栅极结构并用金属栅极结构代替。 在金属栅极结构和掺杂衬底上沉积层间电介质（ILD），并且干蚀刻工艺在ILD中形成到金属栅极结构的顶表面的沟槽。 在干蚀刻工艺之后，湿蚀刻工艺在金属栅极结构的顶表面附近形成底切。 然后用导电材料填充沟槽和底切。