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    Polishing pad and method of making
    1.
    发明申请
    Polishing pad and method of making 审中-公开
    抛光垫和制作方法

    公开(公告)号：US20070204420A1

    公开(公告)日：2007-09-06

    申请号：US11369216

    申请日：2006-03-06

    Applicant: David Hornby ,  Randy Schneider ,  James Testa

    Inventor： David Hornby ,  Randy Schneider ,  James Testa

    IPC: B24D13/14

    CPC classification number: B24B37/24 ,  B24B37/26 ,  B24D7/14

    Abstract: A buffing pad. The buffing pad includes a pad support having a first surface and a second surface; and a resilient foam pad having an attachment surface and a buffing surface, the attachment surface of the resilient foam pad secured to the first surface of the pad support, the resilient foam pad comprising at least two separate concentric rings of resilient foam, the concentric rings being positioned so that there is a gap therebetween. A method of making the buffing pad is also disclosed.

    Abstract translation: 一个抛光垫。 抛光垫包括具有第一表面和第二表面的垫支撑件; 以及弹性泡沫垫，其具有附接表面和抛光表面，所述弹性泡沫垫的附接表面固定到所述垫支撑件的第一表面，所述弹性泡沫垫包括至少两个分开的弹性泡沫的同心环，所述同心环 被定位成使得它们之间存在间隙。 还公开了一种制造抛光垫的方法。

    Printed circuit board attachment mechanism
    2.
    发明授权
    Printed circuit board attachment mechanism 失效
    印刷电路板附件机构

    公开(公告)号：US5434746A

    公开(公告)日：1995-07-18

    申请号：US182440

    申请日：1994-01-13

    Applicant: James Testa ,  Joseph M. Spano ,  William L. Dailey ,  Daniel D. Gonsalves ,  Robert S. Antonuccio ,  James M. Carney ,  Mathew J. Palazola

    Inventor： James Testa ,  Joseph M. Spano ,  William L. Dailey ,  Daniel D. Gonsalves ,  Robert S. Antonuccio ,  James M. Carney ,  Mathew J. Palazola

    IPC: H05K7/14 ,  H05K5/00

    CPC classification number: H05K7/1417

    Abstract: An improved attachment mechanism for attaching the motherboard in a computer system to its chassis is disclosed. The attachment mechanism includes a rail that engages at least two opposing edges of the motherboard and a hook mechanism that engages a catch formed in the chassis. The hook mechanism is secured to a central portion of the motherboard. The rail and hook mechanism cooperate to securely couple the motherboard to the chassis without requiting the use of extensive usable space on the motherboard. The described arrangement permits the motherboard to be quickly and easily installed and released.

    Abstract translation: 公开了一种用于将计算机系统中的主板连接到其底盘的改进的附接机构。 附接机构包括接合母板的至少两个相对边缘的轨道和接合形成在底盘中的挡块的钩机构。 钩机构固定到母板的中心部分。 轨道和钩子机构配合以将主板牢固地连接到底盘，而不需要在主板上使用广泛的可用空间。 所述的布置允许主板快速且容易地安装和释放。

    Bus architecture for integrated data and video memory
    4.
    发明授权
    Bus architecture for integrated data and video memory 失效
    集成数据和视频存储器的总线架构

    公开(公告)号：US5265218A

    公开(公告)日：1993-11-23

    申请号：US886671

    申请日：1992-05-19

    Applicant: James Testa ,  Andreas Behtolsheim ,  Edward Frank ,  Trevor Creary ,  David Emberson ,  Shawn F. Storm ,  Bradley Hoffert

    Inventor： James Testa ,  Andreas Behtolsheim ,  Edward Frank ,  Trevor Creary ,  David Emberson ,  Shawn F. Storm ,  Bradley Hoffert

    IPC: G06F13/16 ,  G06F13/42

    CPC classification number: G06F13/4243 ,  G06F13/1663

    Abstract: A bus architecture and protocol for integrated data and video memory. A high speed dedicated memory bus is coupled to a memory controller. The memory controller is in turn coupled to a multiple processor bus interconnecting one or more processors. Single in-line memory modules (SIMMs) incorporating dynamic random access memory (DRAM), video RAM (VRAM), and static nonvolatile RAM (SRAM) are coupled to the memory bus. Bus control signals forming a bus protocol, and address and data lines from the memory controller are shared by all memory modules operating on the memory bus. Certain control signals invoke specific operations on memory modules or are ignored, depending on the type of memory module receiving the control signal. The memory modules incorporate the consistent protocol by virtue of a consistent control signal pin out. The SIMMs further incorporate buffering and conversion functions, thereby relieving the memory controller of service overhead associated with these functions. Integrating all forms of memory into a single data and video memory architecture permits a highly functional dedicated memory bus to be connected to the computer system.

    Multiple bus architecture for flexible communication among processor modules and memory subsystems and specialized subsystems
    5.
    发明授权
    Multiple bus architecture for flexible communication among processor modules and memory subsystems and specialized subsystems 失效
    多总线架构，用于处理器模块与存储器子系统和专用子系统之间的灵活通信

    公开(公告)号：US5263139A

    公开(公告)日：1993-11-16

    申请号：US886045

    申请日：1992-05-19

    Applicant: James Testa ,  Andreas Bechtolsheim

    Inventor： James Testa ,  Andreas Bechtolsheim

    IPC: G06F13/36 ,  G06F13/14 ,  G06F13/38 ,  G06F13/40 ,  G06F13/16 ,  G06F13/20

    CPC classification number: G06F13/4022 ,  G06F13/14

    Abstract: A multiple bus architecture for flexible communication between processors, memory subsystems, and specialized subsystems over multiple high performance communication pathways. The multiple bus architecture enables flexible communication between processors and devices coupled to a multiprocessor bus, a system interconnect bus, an external bus, an input/output bus, and a memory subsystem. Processor modules coupled to multiprocessor bus slots access the memory subsystem over the multiprocessor bus. System interconnect modules coupled to system interconnect bus slots access the memory subsystem via the system interconnect bus, and the multiprocessor bus. Processor modules coupled to multiprocessor bus slots access devices on the external bus via the system interconnect bus.

    Abstract translation: 多总线架构，用于通过多个高性能通信路径在处理器，存储器子系统和专用子系统之间灵活通信。 多总线架构使得处理器与耦合到多处理器总线，系统互连总线，外部总线，输入/输出总线和存储器子系统之间的灵活通信。 耦合到多处理器总线插槽的处理器模块通过多处理器总线访问存储器子系统。 耦合到系统互连总线插槽的系统互连模块经由系统互连总线和多处理器总线访问存储器子系统。 耦合到多处理器总线插槽的处理器模块通过系统互连总线访问外部总线上的设备。

    Single in-line memory module
    6.
    发明授权
    Single in-line memory module 失效
    单列直插式内存模块

    公开(公告)号：US5383148A

    公开(公告)日：1995-01-17

    申请号：US279824

    申请日：1994-07-25

    Applicant: James Testa ,  Andreas Bechtolsheim ,  Edward Frank ,  Shawn Storm

    Inventor： James Testa ,  Andreas Bechtolsheim ,  Edward Frank ,  Shawn Storm

    IPC: G06F12/06 ,  G06F12/16 ,  G11C5/00 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/40 ,  G11C13/00

    CPC classification number: G11C5/04 ,  G11C5/00 ,  H05K1/117 ,  H05K1/141 ,  H05K1/181 ,  H05K2201/09645 ,  H05K2201/10689 ,  H05K2203/1572 ,  H05K3/403 ,  Y10S439/951

    Abstract: A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions is disclosed. A printed circuit board having a multiplicity of DRAM memory elements mounted thereto is arranged in a data path having a width of 144 bits. The SIMM of the present invention further includes on-board drivers to buffer and drive signals in close proximity to the memory elements. In addition, electrically conductive traces are routed on the circuit board in such a manner to reduce loading and trace capacitance to minimize signal skew to the distributed memory elements. The SIMM further includes a high pin density dual readout connector structure receiving electrical traces from both sides of the circuit board for enhanced functionality. The SIMM is installed in complementary sockets one SIMM at a time to provide memory expansion in full width increments. Finally, symmetrical power and ground routings to the connector structure insure that the SIMM cannot be inserted incorrectly, wherein physically reversing the SIMM in the connector slot will not reverse power the SIMM.

    Abstract translation: 公开了用于动态随机存取存储器（DRAM）存储器扩展的全宽单列直插存储器模块（SIMM）。 具有安装在其上的多个DRAM存储元件的印刷电路板布置在宽度为144位的数据路径中。 本发明的SIMM还包括板载驱动器，用于缓冲和驱动紧邻存储器元件的信号。 此外，导电迹线以这样的方式布线在电路板上，以减少负载和跟踪电容以最小化到分布式存储器元件的信号偏移。 SIMM还包括高引脚密度双读出连接器结构，从电路板的两侧接收电迹线以增强功能。 SIMM一次安装在一个SIMM的互补插座中，以全宽增量提供内存扩展。 最后，连接器结构的对称电源和接地布线确保SIMM不能被错误地插入，其中物理地反转连接器插槽中的SIMM将不会使SIMM反向供电。

    Tracking Frequent Flyer Miles
    7.
    发明申请
    Tracking Frequent Flyer Miles 审中-公开
    跟踪常旅客里程

    公开(公告)号：US20080312950A1

    公开(公告)日：2008-12-18

    申请号：US12186073

    申请日：2008-08-05

    Applicant: James Testa ,  Nina Holly

    Inventor： James Testa ,  Nina Holly

    IPC: G06Q99/00

    CPC classification number: G06Q10/00 ,  G06Q30/00 ,  G06Q30/0226

    Abstract: Inter alia, methods, and means for tracking frequent flyer miles. One embodiment identifies a user database which has a one to many relationship to an accommodations database which contains flights the user has taken along with the corresponding distance traveled in that flight. The distance traveled corresponds to the frequent flyer miles that have been earned for that flight. There is further a vendors database which contains the vendors with which the accommodation occurred with, along with an accommodations_vendors database which indicates which accommodation corresponds to which vendor. With these databases, on a per user basis, the number of frequent flyer miles per user per vendor can be determined. Two other databases allow the determination of the number of frequent flyer miles that can be redeemed for a given vendor based on the number of frequent flyer miles earned on the vendor partners of a given vendor. These two databases are the partners database and the partners_vendors database. Thus the tracking of frequent flyer miles allows the user to determine a) the number of frequent flyer miles that can be redeemed with one vendor based on the trips taken with that vendor, and b) the total number of frequent flyer miles redeemable with a given vendor based on the number of frequent flyer miles earned with all the vendors that are partners with the given vendor.

    Abstract translation: 特别是方法和跟踪常旅客里程的方法。 一个实施例标识用户数据库，该用户数据库与包含用户已经在该飞行中行进的相应距离的航班的住宿数据库具有一对多的关系。 旅行距离对应于该航班已经获得的常旅客里程。 还有一个供应商数据库，其中包含住房所在的供应商，以及一个accommodation_vendors数据库，指示哪个住宿对应于哪个供应商。 利用这些数据库，在每个用户的基础上，可以确定每个供应商每个用户的飞行里程数。 另外两个数据库允许根据给定供应商的供应商合作伙伴获得的飞行里程数确定给定供应商可以兑换的飞行常客里程数。 这两个数据库是合作伙伴数据库和partners_vendors数据库。 因此，经常飞行里程的跟踪允许用户根据与该供应商进行的行程确定a）可以用一个供应商兑换的飞行常客里程的数量，以及b）可以用给定的可兑换的飞行常客里程的总数 供应商基于与给定供应商合作的所有供应商所获得的常旅客里程数。

    Single in-line memory module
    9.
    发明授权
    Single in-line memory module 失效
    单列直插式内存模块

    公开(公告)号：US5465229A

    公开(公告)日：1995-11-07

    申请号：US345477

    申请日：1994-11-28

    Applicant: Andreas Bechtolsheim ,  Edward Frank ,  James Testa ,  Shawn Storm

    Inventor： Andreas Bechtolsheim ,  Edward Frank ,  James Testa ,  Shawn Storm

    IPC: G06F12/06 ,  G06F12/16 ,  G11C5/00 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/40 ,  G11C13/00

    CPC classification number: G11C5/04 ,  G11C5/00 ,  H05K1/117 ,  H05K1/141 ,  H05K1/181 ,  H05K2201/09645 ,  H05K2201/10689 ,  H05K2203/1572 ,  H05K3/403 ,  Y10S439/951

    Abstract: A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions is disclosed. A printed circuit board having a multiplicity of DRAM memory elements mounted thereto is arranged in a data path having a width of 144 bits. The SIMM of the present invention further includes on-board drivers to buffer and drive signals in close proximity to the memory elements. In addition, electrically conductive traces are routed on the circuit board in such a manner to reduce loading and trace capacitance to minimize signal skew to the distributed memory elements. The SIMM further includes a high pin density dual readout connector structure receiving electrical traces from both sides of the circuit board for enhanced functionality. The SIMM is installed in complementary sockets one SIMM, at a time to provide memory expansion in full width increments. Finally, symmetrical power and ground routings to the connector structure insure that the SIMM cannot be inserted incorrectly, wherein physically reversing the SIMM in the connector slot will not reverse power the SIMM.

    Abstract translation: 公开了用于动态随机存取存储器（DRAM）存储器扩展的全宽单列直插存储器模块（SIMM）。 具有安装在其上的多个DRAM存储元件的印刷电路板布置在宽度为144位的数据路径中。 本发明的SIMM还包括板载驱动器，用于缓冲和驱动紧邻存储器元件的信号。 此外，导电迹线以这样的方式布线在电路板上，以减少负载和跟踪电容以最小化到分布式存储器元件的信号偏移。 SIMM还包括高引脚密度双读出连接器结构，从电路板的两侧接收电迹线以增强功能。 SIMM安装在一个SIMM的互补插座中，以提供全宽度增量的内存扩展。 最后，连接器结构的对称电源和接地布线确保SIMM不能被错误地插入，其中物理地反转连接器插槽中的SIMM将不会使SIMM反向供电。

    Expense Report Generation From Confirmation Emails
    10.
    发明申请
    Expense Report Generation From Confirmation Emails 审中-公开
    从确认电子邮件生成费用报表

    公开(公告)号：US20080313063A1

    公开(公告)日：2008-12-18

    申请号：US12186131

    申请日：2008-08-05

    Applicant: James Testa ,  Nina Holly

    Inventor： James Testa ,  Nina Holly

    IPC: G06Q30/00

    CPC classification number: G06Q10/107 ,  G06Q40/12

    Abstract: Inter alia, methods, and means for automatically generated travel expense reports. One embodiment identifies an email extractor that reads travel expense information from travel reservation booking emails. The extracted information is then displayed in electronic table format. The displayed information includes travel expense details such as vendor name, trip conveyance, date of reservation/expense, accommodation name, cost, currency, etc. The expense report can be accessed and edited by the user, if desired. The user can view and download the report in other formats, such as a spreadsheet.

    Abstract translation: 特别是自动生成旅行费用报告的方法和手段。 一个实施例识别从旅行预订电子邮件读取旅行费用信息的电子邮件提取器。 然后以电子表格格式显示所提取的信息。 所显示的信息包括诸如供应商名称，旅行转运，预约/支出日期，住宿名称，费用，货币等的旅行费用细节。如果需要，费用报告可以由用户访问和编辑。 用户可以以其他格式（如电子表格）查看和下载报告。

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