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    PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES
    1.
    发明申请
    PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES 有权
    具有双读模式的处理器指令高速缓存

    公开(公告)号：US20120014196A1

    公开(公告)日：2012-01-19

    申请号：US13245551

    申请日：2011-09-26

    Applicant: Sehat Sutardja ,  Jason T. Su ,  Hong-Yi Chen ,  Jason Sheu ,  Jensen Tjeng

    Inventor： Sehat Sutardja ,  Jason T. Su ,  Hong-Yi Chen ,  Jason Sheu ,  Jensen Tjeng

    IPC: G11C7/12 ,  G11C7/00

    CPC classification number: G06F12/0882 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/3804 ,  G06F9/3844 ,  G11C7/06 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/22 ,  G11C2207/2245 ,  G11C2207/2281 ,  Y02D10/13

    Abstract: A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second instructions stored in the first word line or a second word line. The precharge circuit (i) precharges first bit lines connected to the first word line prior to accessing each of the first and second instructions. The control module adjusts a rate of a clock signal from a first rate to a second rate. The amplifier module accesses the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and accesses the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate.

    Abstract translation: 一种包括高速缓冲存储器，解码器，预充电电路，控制模块和放大器模块的处理器。 解码器产生第一字线信号以访问存储在第一字线中的第一指令，以及（ii）产生第二字线信号以访问存储在第一字线或第二字线中的第二指令。 预充电电路（i）在访问第一和第二指令中的每一个之前预先连接到第一字线的第一位线。 控制模块将时钟信号的速率从第一速率调整到第二速率。 放大器模块基于（i）第一字线信号和（ii）以第一速率的时钟信号来访问第一指令，并且基于（i）第二字线信号和（ii）时钟来访问第二指令 以第二速率发出信号。

    Processor instruction cache with dual-read modes
    2.
    发明授权
    Processor instruction cache with dual-read modes 有权
    具有双读模式的处理器指令缓存

    公开(公告)号：US08089823B2

    公开(公告)日：2012-01-03

    申请号：US12868341

    申请日：2010-08-25

    Applicant: Sehat Sutardja ,  Jason T. Su ,  Hong-Yi Chen ,  Jason Sheu ,  Jensen Tjeng

    Inventor： Sehat Sutardja ,  Jason T. Su ,  Hong-Yi Chen ,  Jason Sheu ,  Jensen Tjeng

    IPC: G11C8/00

    CPC classification number: G11C7/1045 ,  G06F12/0877 ,  G06F12/0882 ,  G06F12/0893 ,  G06F2212/1028 ,  G11C7/1027 ,  G11C7/12 ,  G11C11/418 ,  G11C2207/104 ,  G11C2207/2245 ,  Y02D10/13

    Abstract: A processor including a memory and a control module. The memory has an array of cells. The control module is configured to: determine a number of access cycles along a first word line; determine an extended period based on the number of the access cycles; generate a word line signal to maintain the first word line in an activated state during (i) an initial period and (ii) the extended period; and access a first cell during the extended period. The first cell is connected to the first word line. The control module is further configured to deactivate the word line and maintain the first word line in a deactivated state while accessing a second cell connected to the first word line. The accessing of the second cell is based on a bit line separation provided during the extended period.

    Abstract translation: 一种包括存储器和控制模块的处理器。 内存有一个单元格阵列。 控制模块被配置为：沿着第一字线确定多个访问周期; 基于访问周期的数量确定延长的周期; 生成字线信号以在（i）初始期间和（ii）延长期间内将第一字线维持在激活状态; 并在长时间内访问第一个单元。 第一个单元格连接到第一个字线。 控制模块还被配置为在访问连接到第一字线的第二单元时停用字线并将第一字线保持在去激活状态。 第二小区的访问是基于在延长的时间段内提供的位线分离。

    Processor instruction cache with dual-read modes
    5.
    发明授权
    Processor instruction cache with dual-read modes 有权
    具有双读模式的处理器指令缓存

    公开(公告)号：US08295110B2

    公开(公告)日：2012-10-23

    申请号：US13245551

    申请日：2011-09-26

    Applicant: Sehat Sutardja ,  Jason T. Su ,  Hong-Yi Chen ,  Jason Sheu ,  Jensen Tjeng

    Inventor： Sehat Sutardja ,  Jason T. Su ,  Hong-Yi Chen ,  Jason Sheu ,  Jensen Tjeng

    IPC: G11C7/00

    CPC classification number: G06F12/0882 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/3804 ,  G06F9/3844 ,  G11C7/06 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/22 ,  G11C2207/2245 ,  G11C2207/2281 ,  Y02D10/13

    Abstract: A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second instructions stored in the first word line or a second word line. The precharge circuit (i) precharges first bit lines connected to the first word line prior to accessing each of the first and second instructions. The control module adjusts a rate of a clock signal from a first rate to a second rate. The amplifier module accesses the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and accesses the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate.

    Abstract translation: 一种包括高速缓冲存储器，解码器，预充电电路，控制模块和放大器模块的处理器。 解码器产生第一字线信号以访问存储在第一字线中的第一指令，以及（ii）产生第二字线信号以访问存储在第一字线或第二字线中的第二指令。 预充电电路（i）在访问第一和第二指令中的每一个之前预先连接到第一字线的第一位线。 控制模块将时钟信号的速率从第一速率调整到第二速率。 放大器模块基于（i）第一字线信号和（ii）以第一速率的时钟信号来访问第一指令，并且基于（i）第二字线信号和（ii）时钟来访问第二指令 以第二速率发出信号。

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