公开(公告)号：US06658728B2

公开(公告)日：2003-12-09

申请号：US09917572

申请日：2001-07-27

Applicant: David Kirtland Fork ,  Jackson Ho ,  Rachel King-ha Lau ,  JengPing Lu

Inventor： David Kirtland Fork ,  Jackson Ho ,  Rachel King-ha Lau ,  JengPing Lu

IPC: H05K330

CPC classification number: G01R1/06716 ,  B81B2203/0118 ,  B81C1/00484 ,  B81C2201/0136 ,  B81C2203/058 ,  G01R1/06727 ,  G01R1/07342 ,  G01R3/00 ,  H01L23/49811 ,  H01L2924/0002 ,  H01R4/48 ,  H01R12/57 ,  H05K3/4092 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/4914 ,  H01L2924/00

Abstract: Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad/via.

Abstract translation: 通过使用单个掩模通过形成弹簧金属和释放材料层来将含有接触垫或金属通孔的弹性结构光刻制造到衬底上的有效方法。 具体地说，使用光致抗蚀剂掩模或电镀金属图案或使用剥离处理技术，释放材料垫与弹簧金属手指自对准。 然后使用释放掩模释放弹簧金属指，同时保持将弹簧金属指的锚固部分固定到基底的释放材料的一部分。 当释放材料是导电的（例如钛）时，该释放材料部分直接位于接触垫或金属通孔上方，并且用作在完成的弹簧结构中的弹簧金属指的导管。 当释放材料不导电时，形成金属带以将弹簧金属手指连接到接触垫/通孔。

公开(公告)号：US06361331B1

公开(公告)日：2002-03-26

申请号：US09923600

申请日：2001-08-06

Applicant: David Kirtland Fork ,  Jackson Ho ,  Rachel King-ha Lau ,  JengPing Lu

Inventor： David Kirtland Fork ,  Jackson Ho ,  Rachel King-ha Lau ,  JengPing Lu

IPC: H01R909

Abstract: Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad or metal via, and also to further anchor the spring metal finger to the substrate.

公开(公告)号：US09961771B2

公开(公告)日：2018-05-01

申请号：US13571252

申请日：2012-08-09

Applicant: JengPing Lu ,  Eugene M. Chow

Inventor： JengPing Lu ,  Eugene M. Chow

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/36

CPC classification number: H05K1/142 ,  H05K1/0286 ,  H05K1/14 ,  H05K3/368 ,  H05K2201/09963 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A method of forming an interconnect substrate includes providing at least two unit cells, arranging the unit cells to form a desired circuit pattern, and joining the unit cells to form the interconnect substrate having the desired circuit pattern.

公开(公告)号：US07863703B2

公开(公告)日：2011-01-04

申请号：US12379581

申请日：2009-02-25

Applicant: JengPing Lu ,  James B. Boyce ,  Kathleen Dore Boyce, legal representative

Inventor： JengPing Lu ,  James B. Boyce

IPC: H01L29/868 ,  H01L31/105

CPC classification number: H01L27/1446 ,  H01L31/105

Abstract: A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

Abstract translation: 形成高填充因子光电传感器阵列，其包括P层，I层，与I层相邻并且各自耦合到N层的一个或多个半导体结构，形成在P的顶部上的导电电极 以及与N层相邻并且与电压偏置源电连接的附加半导体结构。 施加到附加半导体结构的偏置电压对附加的半导体结构进行充电，从而在N层和P层之间产生隧穿效应，其中电子离开N层并到达P层和导电层。 电子然后在整个导电层中均匀迁移和均匀分布，这确保跨越整个光电传感器阵列的均匀偏压。 本发明的偏置方案允许在不使用引线接合的情况下实现光电传感器的批量生产。

公开(公告)号：US20090160006A1

公开(公告)日：2009-06-25

申请号：US12379581

申请日：2009-02-25

Applicant: JengPing Lu ,  James B. Boyce ,  Kathleen Dore Boyce

Inventor： JengPing Lu ,  James B. Boyce ,  Kathleen Dore Boyce

IPC: H01L31/105 ,  H03K3/01

CPC classification number: H01L27/1446 ,  H01L31/105

Abstract: A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

Abstract translation: 形成高填充因子光电传感器阵列，其包括P层，I层，与I层相邻并且各自耦合到N层的一个或多个半导体结构，形成在P的顶部上的导电电极 以及与N层相邻并且与电压偏置源电连接的附加半导体结构。 施加到附加半导体结构的偏置电压对附加的半导体结构进行充电，从而在N层和P层之间产生隧穿效应，其中电子离开N层并到达P层和导电层。 电子然后在整个导电层中均匀迁移和均匀分布，这确保跨越整个光电传感器阵列的均匀偏压。 本发明的偏置方案允许在不使用引线接合的情况下实现光电传感器的批量生产。

公开(公告)号：US20080141877A1

公开(公告)日：2008-06-19

申请号：US11613159

申请日：2006-12-19

Applicant: Dirk De Bruyker ,  JengPing Lu ,  Jurgen H. Daniel ,  Eugene M. Chow ,  Armin R. Volkel

Inventor： Dirk De Bruyker ,  JengPing Lu ,  Jurgen H. Daniel ,  Eugene M. Chow ,  Armin R. Volkel

IPC: B41M1/10

CPC classification number: B41M1/10 ,  B41M1/04 ,  B41M1/06 ,  H05K3/207 ,  H05K2201/091 ,  H05K2203/105

Abstract: A printing surface includes a substrate having latching electrodes on a first surface, a spacer layer on the first surface of the substrate, the spacer layer patterned to form wells such that the latching electrodes reside in the wells, a deformable membrane, the membrane having conductive regions, on the spacer layer to enclose the wells, each enclosed well and its associated region of the membrane forming a pixel membrane, and actuation circuitry to actuate the electrodes to cause selected ones of the pixel membranes to remain in a deflected state when the pixel membranes receive an impulse to return to an undeflected state.

Abstract translation: 打印表面包括在第一表面上具有锁定电极的基板，在基板的第一表面上的间隔层，图案化的间隔层以形成孔，使得锁定电极驻留在孔中，可变形的膜，该膜具有导电 区域，在间隔层上包围孔，每个封闭的井及其膜的相关区域形成像素膜，以及致动电路，用于致动电极，以使像素膜中选定的像素膜保持在偏转状态，当像素 膜受到冲击以返回到未偏转的状态。

公开(公告)号：US07227237B2

公开(公告)日：2007-06-05

申请号：US10740466

申请日：2003-12-22

Applicant: JengPing Lu ,  Kathleen Dore Boyce, legal representative

Inventor： James B. Boyce, deceased

IPC: H01L31/00

CPC classification number: H01L27/1446 ,  H01L31/105

Abstract: A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

Abstract translation: 形成高填充因子光电传感器阵列，其包括P层，I层，与I层相邻并且各自耦合到N层的一个或多个半导体结构，形成在P的顶部上的导电电极 以及与N层相邻并且与电压偏置源电连接的附加半导体结构。 施加到附加半导体结构的偏置电压对附加的半导体结构进行充电，从而在N层和P层之间产生隧穿效应，其中电子离开N层并到达P层和导电层。 电子然后在整个导电层中均匀迁移和均匀分布，这确保跨越整个光电传感器阵列的均匀偏压。 本发明的偏置方案允许在不使用引线接合的情况下实现光电传感器的批量生产。

公开(公告)号：US08283566B2

公开(公告)日：2012-10-09

申请号：US12404294

申请日：2009-03-14

Applicant: JengPing Lu ,  Eugene M. Chow

Inventor： JengPing Lu ,  Eugene M. Chow

IPC: H05K1/00

CPC classification number: H05K1/142 ,  H05K1/0286 ,  H05K1/14 ,  H05K3/368 ,  H05K2201/09963 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A method of forming an interconnect substrate includes providing at least two unit cells, arranging the unit cells to form a desired circuit pattern, and joining the unit cells to form the interconnect substrate having the desired circuit pattern. A circuit substrate, has a desired circuit pattern on a substrate, the substrate made up of at least two unit cells having conductive lines electrically connected together.

Abstract translation: 形成互连衬底的方法包括提供至少两个单元电池，布置单元电池以形成期望的电路图案，以及连接单元电池以形成具有所需电路图案的互连衬底。 电路基板在基板上具有期望的电路图案，该基板由具有电连接在一起的导电线的至少两个单电池构成。

公开(公告)号：US20110107928A1

公开(公告)日：2011-05-12

申请号：US12957113

申请日：2010-11-30

Applicant: Dirk De Bruyker ,  JengPing Lu ,  Jürgen H. Daniel ,  Eugene M. Chow ,  Armin R. Völkel

Inventor： Dirk De Bruyker ,  JengPing Lu ,  Jürgen H. Daniel ,  Eugene M. Chow ,  Armin R. Völkel

IPC: B41M1/10

CPC classification number: B41M1/10 ,  B41M1/04 ,  B41M1/06 ,  H05K3/207 ,  H05K2201/091 ,  H05K2203/105

Abstract: A printing surface includes a substrate having latching electrodes on a first surface, a spacer layer on the first surface of the substrate, the spacer layer patterned to form wells such that the latching electrodes reside in the wells, a deformable membrane, the membrane having conductive regions, on the spacer layer to enclose the wells, each enclosed well and its associated region of the membrane forming a pixel membrane, and actuation circuitry to actuate the electrodes to cause selected ones of the pixel membranes to remain in a deflected state when the pixel membranes receive an impulse to return to an undeflected state.

Abstract translation: 打印表面包括在第一表面上具有锁定电极的基板，在基板的第一表面上的间隔层，图案化的间隔层以形成孔，使得锁定电极驻留在孔中，可变形的膜，该膜具有导电 区域，在间隔层上包围孔，每个封闭的井及其膜的相关区域形成像素膜，以及致动电路，用于致动电极，以使像素膜中选定的像素膜保持在偏转状态，当像素 膜受到冲击以返回到未偏转的状态。

公开(公告)号：US20100230139A1

公开(公告)日：2010-09-16

申请号：US12404294

申请日：2009-03-14

Applicant: JengPing Lu ,  Eugene M. Chow

Inventor： JengPing Lu ,  Eugene M. Chow

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/142 ,  H05K1/0286 ,  H05K1/14 ,  H05K3/368 ,  H05K2201/09963 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A method of forming an interconnect substrate includes providing at least two unit cells, arranging the unit cells to form a desired circuit pattern, and joining the unit cells to form the interconnect substrate having the desired circuit pattern. A circuit substrate, has a desired circuit pattern on a substrate, the substrate made up of at least two unit cells having conductive lines electrically connected together.

Abstract translation: 形成互连衬底的方法包括提供至少两个单元电池，布置单元电池以形成期望的电路图案，以及连接单元电池以形成具有所需电路图案的互连衬底。 电路基板在基板上具有期望的电路图案，该基板由具有电连接在一起的导电线的至少两个单电池构成。