公开(公告)号：US09454371B2

公开(公告)日：2016-09-27

申请号：US13977064

申请日：2012-10-04

Applicant: Venkateswara Madduri ,  Jonathan Combs ,  James E. Phillips ,  Stephen J. Robinson ,  James D. Allen ,  Jonathan J. Tyler

Inventor： Venkateswara Madduri ,  Jonathan Combs ,  James E. Phillips ,  Stephen J. Robinson ,  James D. Allen ,  Jonathan J. Tyler

IPC: G06F9/315 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

Abstract: A computer system and processor for elimination of move operations include circuits that obtain a computer instruction and bypass execution units in response to determining that the instruction includes a move operation that involves a transfer of data from a logical source register to a logical destination register. Instead of executing the move operation, the transfer of the data is performed by tracking changes in data dependencies of the source and the destination registers, and assigning a physical register associated with the source register to the destination register based on the dependencies.

Abstract translation: 用于消除移动操作的计算机系统和处理器包括响应于确定该指令包括涉及将数据从逻辑源寄存器传送到逻辑目标寄存器的移动操作而获得计算机指令和旁路执行单元的电路。 代替执行移动操作，通过跟踪源和目的地寄存器的数据相关性的变化以及基于依赖性将与源寄存器相关联的物理寄存器分配给目的寄存器来执行数据的传送。

公开(公告)号：US08656108B2

公开(公告)日：2014-02-18

申请号：US13551565

申请日：2012-07-17

Applicant: Martin Licht ,  Jonathan Combs ,  Andrew Huang

Inventor： Martin Licht ,  Jonathan Combs ,  Andrew Huang

IPC: G06F12/00

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F9/3806 ,  G06F9/3814 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

公开(公告)号：US20050071518A1

公开(公告)日：2005-03-31

申请号：US10677039

申请日：2003-09-30

Applicant: Nicholas Samra ,  Stephan Jourdan ,  Jonathan Combs ,  Avinash Sodani ,  Per Hammarlund ,  Michael Cornaby

Inventor： Nicholas Samra ,  Stephan Jourdan ,  Jonathan Combs ,  Avinash Sodani ,  Per Hammarlund ,  Michael Cornaby

IPC: G06F3/00 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30094 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

Abstract: According to an embodiment of the invention, a method and apparatus for flag value renaming. An embodiment of a method comprises setting a flag for a processor via a first instruction, the first instruction being either a direct update instruction or an indirect update instruction; if the setting of the flag is by a direct update instruction, executing a succeeding second instruction that reads the flag prior to completion of the first instruction; and if the setting of the flag is by an indirect update instruction, delaying the second instruction until after completion of the first instruction.

Abstract translation: 根据本发明的实施例，一种用于标志值重命名的方法和装置。 方法的实施例包括经由第一指令设置处理器的标志，第一指令是直接更新指令或间接更新指令; 如果所述标志的设置是通过直接更新指令，则执行在完成所述第一指令之前读取所述标志的后续第二指令; 并且如果所述标志的设置是通过间接更新指令，则延迟所述第二指令直到所述第一指令完成为止。

公开(公告)号：US20140068230A1

公开(公告)日：2014-03-06

申请号：US13977064

申请日：2012-10-04

Applicant: Venkateswara Madduri ,  Jonathan Combs ,  James E. Phillips ,  Stephen J. Robinson ,  James D. Allen ,  Jonathan J. Tyler

Inventor： Venkateswara Madduri ,  Jonathan Combs ,  James E. Phillips ,  Stephen J. Robinson ,  James D. Allen ,  Jonathan J. Tyler

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

Abstract: A computer system and processor for elimination of move operations include circuits that obtain a computer instruction and bypass execution units in response to determining that the instruction includes a move operation that involves a transfer of data from a logical source register to a logical destination register. Instead of executing the move operation, the transfer of the data is performed by tracking changes in data dependencies of the source and the destination registers, and assigning a physical register associated with the source register to the destination register based on the dependencies.

Abstract translation: 用于消除移动操作的计算机系统和处理器包括响应于确定该指令包括涉及将数据从逻辑源寄存器传送到逻辑目标寄存器的移动操作而获得计算机指令和旁路执行单元的电路。 代替执行移动操作，通过跟踪源和目的地寄存器的数据相关性的变化以及基于依赖性将与源寄存器相关联的物理寄存器分配给目的寄存器来执行数据的传送。

公开(公告)号：US20120284462A1

公开(公告)日：2012-11-08

申请号：US13551565

申请日：2012-07-17

Applicant: Martin Licht ,  Jonathan Combs ,  Andrew Huang

Inventor： Martin Licht ,  Jonathan Combs ,  Andrew Huang

IPC: G06F12/08

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F9/3806 ,  G06F9/3814 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

Abstract translation: 这里描述了用于响应于基于历史的使用模式来禁用缓存存储器的方式的方法和装置。 方式预测逻辑是跟踪高速缓存访​​问的方式，并确定是否要禁用某些方式的访问以节省功率，这是基于具有表示预测错过的逻辑状态的功率信号的方式。 与方式计数访问相关联的一个或多个计数器，其中当所述一个或多个计数器之一达到饱和值时，功率信号被设置为表示预测的未命中的逻辑状态。 控制逻辑根据访问方式来调整与一些或多个计数器相关联的方式。

公开(公告)号：US08225046B2

公开(公告)日：2012-07-17

申请号：US11541174

申请日：2006-09-29

Applicant: Martin Licht ,  Jonathan Combs ,  Andrew Huang

Inventor： Martin Licht ,  Jonathan Combs ,  Andrew Huang

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F9/3806 ,  G06F9/3814 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to track consecutive misses to ways of a cache, i.e. hits/reads to other ways of cache. Based on the usage of ways and the non-usage of other ways, the way predicting logic determines if a way is to be powered down. In response to determining a way is to be powered down, the way predicting logic generates a power signal to power down an associated. Furthermore, upon a subsequent hit to a powered down way, the way predicting logic toggles the power signal to power up the associated way to ensure performance.

Abstract translation: 这里描述了用于响应于基于历史的使用模式来禁用缓存存储器的方式的方法和装置。 预测逻辑的方式是跟踪缓存的方式的连续丢失，即对其他缓存方式的命中/读取。 基于使用方法和不使用其他方法，预测逻辑的方式决定了一种方式是否被关闭。 响应于确定要断电的方式，预测逻辑的方式产生功率信号以关断相关联的功率。 此外，在随后的电源关断方式下，预测逻辑的方式切换电源信号以加电相关联的方式以确保性能。

公开(公告)号：US20240220260A1

公开(公告)日：2024-07-04

申请号：US18091599

申请日：2022-12-30

Applicant: Jason AGRON ,  Ching-Tsun CHOU ,  Sebastian WINKEL ,  Tyler SONDAG ,  David SHEFFIELD ,  Leela Kamalesh YADLAPALLI ,  Yipeng WANG ,  Jonathan COMBS ,  Jeff WIEDEMEIER

Inventor： Jason AGRON ,  Ching-Tsun CHOU ,  Sebastian WINKEL ,  Tyler SONDAG ,  David SHEFFIELD ,  Leela Kamalesh YADLAPALLI ,  Yipeng WANG ,  Jonathan COMBS ,  Jeff WIEDEMEIER

IPC: G06F9/30

CPC classification number: G06F9/30185 ,  G06F9/30189 ,  G06F9/30196

Abstract: Techniques for accessing 32 general purpose registers, suppressing flags, and/or using a new data destination for an instance of a single instruction are described. An example of a single instruction to at least include a prefix and an opcode to indicate execution circuitry is to do perform a particular operation, wherein the prefix comprises at least two bytes and a second of the two bytes of the prefix is to provide most significant bits for at least register identifier.

公开(公告)号：US20130219205A1

公开(公告)日：2013-08-22

申请号：US13843885

申请日：2013-03-15

Applicant: Martin Licht ,  Jonathan Combs ,  Andrew Huang

Inventor： Martin Licht ,  Jonathan Combs ,  Andrew Huang

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F9/3806 ,  G06F9/3814 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

Abstract translation: 这里描述了用于响应于基于历史的使用模式来禁用缓存存储器的方式的方法和装置。 方式预测逻辑是跟踪高速缓存访​​问的方式，并确定是否要禁用某些方式的访问以节省功率，这是基于具有表示预测错过的逻辑状态的功率信号的方式。 与方式计数访问相关联的一个或多个计数器，其中当所述一个或多个计数器之一达到饱和值时，功率信号被设置为表示预测的未命中的逻辑状态。 控制逻辑根据访问方式来调整与一些或多个计数器相关联的方式。

公开(公告)号：US20080082753A1

公开(公告)日：2008-04-03

申请号：US11541174

申请日：2006-09-29

Applicant: Martin Licht ,  Jonathan Combs ,  Andrew Huang

Inventor： Martin Licht ,  Jonathan Combs ,  Andrew Huang

IPC: G06F12/00

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F9/3806 ,  G06F9/3814 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to track consecutive misses to ways of a cache, i.e. hits/reads to other ways of cache. Based on the usage of ways and the non-usage of other ways, the way predicting logic determines if a way is to be powered down. In response to determining a way is to be powered down, the way predicting logic generates a power signal to power down an associated. Furthermore, upon a subsequent hit to a powered down way, the way predicting logic toggles the power signal to power up the associated way to ensure performance.

Abstract translation: 这里描述了用于响应于基于历史的使用模式来禁用缓存存储器的方式的方法和装置。 预测逻辑的方式是跟踪缓存的方式的连续丢失，即对其他缓存方式的命中/读取。 基于使用方法和不使用其他方法，预测逻辑的方式决定了一种方式是否被关闭。 响应于确定要断电的方式，预测逻辑的方式产生功率信号以关断相关联的功率。 此外，在随后的电源关断方式下，预测逻辑的方式切换电源信号以加电相关联的方式以确保性能。