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    Memory circuit with a bistable circuit and a non-volatile element
    1.
    发明授权
    Memory circuit with a bistable circuit and a non-volatile element 有权

    公开(公告)号：US10049740B2

    公开(公告)日：2018-08-14

    申请号：US15501247

    申请日：2015-08-06

    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY ,  KANAGAWA ACADEMY OF SCIENCE AND TECHNOLOGY

    Inventor： Satoshi Sugahara ,  Yusuke Shuto ,  Shuichiro Yamamoto

    IPC: G11C11/00 ,  G11C14/00 ,  G11C11/419 ,  G11C11/16

    Abstract: A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.

    CATALYST LAYER FOR GAS DIFFUSION ELECTRODE, METHOD FOR MANUFACTURING THE SAME, MEMBRANE ELECTRODE ASSEMBLY, AND FUEL CELL
    3.
    发明申请
    CATALYST LAYER FOR GAS DIFFUSION ELECTRODE, METHOD FOR MANUFACTURING THE SAME, MEMBRANE ELECTRODE ASSEMBLY, AND FUEL CELL 有权
    用于气体扩散电极的催化层，其制造方法，膜电极组件和燃料电池

    公开(公告)号：US20150099207A1

    公开(公告)日：2015-04-09

    申请号：US14505848

    申请日：2014-10-03

    Applicant: Tokyo Institute of Technology ,  Kanagawa Academy of Science and Technology

    Inventor： Takeo YAMAGUCHI ,  Shun OGURA ,  Takanori TAMAKI ,  Teruaki FUCHIGAMI ,  Yoshitaka KITAMOTO ,  Hidenori KUROKI

    IPC: H01M4/92 ,  H01M8/10 ,  H01M4/88 ,  H01M4/86

    CPC classification number: H01M4/928 ,  H01M4/8663 ,  H01M4/9041 ,  H01M4/9091 ,  H01M4/921 ,  H01M8/1004 ,  Y02P70/56

    Abstract: Provided is a catalyst layer for gas diffusion electrode that can be used without using carbon supports, a method for manufacturing the same, a membrane electrode assembly, and a fuel cell. The catalyst layer for gas diffusion electrode according to the present invention include a network-like metallic catalyst formed of a sintered body, the network-like metallic catalyst including nanoparticles linked with each other to have electron conductivity; and an ion conductor, at least a part of the ion conductor contacting the network-like metallic catalyst. Further, the membrane electrode assembly according to the present invention includes a polymer electrolyte membrane provided between an anode catalyst layer and cathode catalyst layer, and the catalyst layer for gas diffusion electrode stated above is used in at least one of the anode catalyst layer and the cathode catalyst layer.

    Abstract translation: 提供了可以不使用碳载体使用的气体扩散电极用催化剂层，其制造方法，膜电极接合体和燃料电池。 根据本发明的气体扩散电极用催化剂层包括由烧结体形成的网状金属催化剂，所述网状金属催化剂包含彼此连接以具有电子传导性的纳米颗粒; 和离子导体，离子导体的至少一部分与网状金属催化剂接触。 此外，根据本发明的膜电极组件包括设置在阳极催化剂层和阴极催化剂层之间的聚合物电解质膜，并且上述用于气体扩散电极的催化剂层用于至少一个阳极催化剂层和 阴极催化剂层。

    MEMORY CIRCUIT
    5.
    发明申请
    MEMORY CIRCUIT 审中-公开

    公开(公告)号：US20170229179A1

    公开(公告)日：2017-08-10

    申请号：US15501247

    申请日：2015-08-06

    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY ,  KANAGAWA ACADEMY OF SCIENCE AND TECHNOLOGY

    Inventor： Satoshi Sugahara ,  Yusuke Shuto ,  Shuichiro Yamamoto

    IPC: G11C14/00 ,  G11C11/16 ,  G11C11/419

    CPC classification number: G11C14/0081 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/412 ,  G11C11/419

    Abstract: A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.

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