公开(公告)号：US20120166766A1

公开(公告)日：2012-06-28

申请号：US12978471

申请日：2010-12-24

Applicant: Jonathan D. Combs ,  Kameswar Subramaniam

Inventor： Jonathan D. Combs ,  Kameswar Subramaniam

IPC: G06F9/28 ,  G06F9/30

CPC classification number: G06F9/28 ,  G06F9/26 ,  G06F9/262 ,  G06F9/30

Abstract: Methods and apparatus for enhanced microcode address stack pointer manipulation are described. In one embodiment, the stacks are invisible to software. In an embodiment, a microcode instruction pointer (UIP) and a next address to be accessed in a microcode storage unit are generated based on an opcode of a microoperation, a marker, and a UIP stack address. The UIP stack address may be generated based on a signal and an immediate field of the microoperation. Other embodiments are also claimed and disclosed.

Abstract translation: 描述了用于增强的微代码地址堆栈指针操纵的方法和装置。 在一个实施例中，堆栈对于软件是不可见的。 在一个实施例中，微代码指令指针（UIP）和在微代码存储单元中要访问的下一个地址基于微操作的操作码，标记和UIP堆栈地址生成。 可以基于微操作的信号和立即字段来生成UIP堆栈地址。 还要求和公开其它实施例。

公开(公告)号：US20240329993A1

公开(公告)日：2024-10-03

申请号：US18193232

申请日：2023-03-30

Applicant: Kameswar SUBRAMANIAM ,  Jason W. BRANDT ,  Gilbert NEIGER

Inventor： Kameswar SUBRAMANIAM ,  Jason W. BRANDT ,  Gilbert NEIGER

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/30101 ,  G06F9/30185

Abstract: Techniques for allowing a control and/or status register to be read or written to in a user privilege level are described. An example of an instruction for user privilege read is to include one or more fields for an opcode, one or more fields for a source operand that is to store a control and/or status register address, and one or more fields for a destination register operand, wherein the opcode is to indicate that execution circuitry is to read data from the control and/or status register whose identity is stored in the source operand and write the data in the destination register operand responsive to access to the control and/or status register being allowed, wherein access to the control and/or status register is at least in part determined by data of an operating system controlled data structure indexed by the control and/or status register address.

公开(公告)号：US20120079248A1

公开(公告)日：2012-03-29

申请号：US12890292

申请日：2010-09-24

Applicant: Jonathan D. Combs ,  Kameswar Subramaniam ,  Jason Brandt

Inventor： Jonathan D. Combs ,  Kameswar Subramaniam ,  Jason Brandt

IPC: G06F9/30 ,  G06F9/22

CPC classification number: G06F9/384 ,  G06F9/226 ,  G06F9/26 ,  G06F9/30145 ,  G06F9/3824 ,  G06F9/4484

Abstract: An apparatus of an aspect includes a plurality of microcode alias locations and a microcode storage. A microinstruction of a microcode subroutine is stored in the microcode storage. The microinstruction has an indication of a microcode alias location. A microcode caller of the microcode subroutine is also stored in the microcode storage. The microcode caller is operable to specify a location of a parameter in the microcode alias location that is indicated by the microinstruction of the microcode subroutine. The apparatus also includes parameter location determination logic that is coupled with the microcode alias locations. The parameter location determination logic is operable, responsive to the microinstruction of the microcode subroutine, to receive the indication of the microcode alias location from the microinstruction and determine the location of the parameter specified in the microcode alias location indicated by the microinstruction.

Abstract translation: 一个方面的装置包括多个微码别名位置和微码存储器。 微代码子程序的微指令存储在微代码存储器中。 微指令具有微代码位置的指示。 微码子程序的微代码调用者也存储在微代码存储器中。 微代码调用者可操作地指定由微代码子程序的微指令指示的微代码别名位置中的参数的位置。 该装置还包括与微码别名位置耦合的参数位置确定逻辑。 参数位置确定逻辑可操作以响应于微代码子程序的微指令，从微指令接收微码别名位置的指示，并确定由微指令指示的微码别名位置中指定的参数的位置。

公开(公告)号：US20240329992A1

公开(公告)日：2024-10-03

申请号：US18193226

申请日：2023-03-30

Applicant: Kameswar Subramaniam ,  Jason Brandt

Inventor： Kameswar Subramaniam ,  Jason Brandt

IPC: G06F9/30

CPC classification number: G06F9/3016

Abstract: Techniques for providing and using a 32-bit immediate in an instruction are described. In some examples, an instance of a single instruction is to include one or more fields for an opcode, one or more fields for one or more operands, one or more fields for a prefix, and a field for an immediate value, wherein the opcode is to indicate one or more operations to be performed using the operands and the prefix is to indicate support for use of the immediate value during execution of the instance of the single instruction.

公开(公告)号：US20160259644A1

公开(公告)日：2016-09-08

申请号：US14639004

申请日：2015-03-04

Applicant: Jason W. Brandt ,  Vedvyas Shanbhogue ,  Kameswar Subramaniam

Inventor： Jason W. Brandt ,  Vedvyas Shanbhogue ,  Kameswar Subramaniam

IPC: G06F9/30

CPC classification number: G06F9/30189 ,  G06F9/30076 ,  G06F9/30145

Abstract: In one embodiment, software executing on a data processing system that is capable of performing dynamic operational mode transitions can realize performance improvements by predicting transitions between modes and/or predicting aspects of a new operational mode. Such prediction can allow the processor to begin an early transition into the target mode. The mode transition prediction principles can be applied for various processor mode transitions including 64-bit to 32-bit mode transitions, interrupts, exceptions, traps, virtualization mode transfers, system management mode transfers, and/or secure execution mode transfers.

Abstract translation: 在一个实施例中，在能够执行动态操作模式转换的数据处理系统上执行的软件可以通过预测模式之间的转换和/或预测新的操作模式的方面来实现性能改进。 这种预测可以允许处理器开始早期转换到目标模式。 模式转换预测原理可以应用于各种处理器模式转换，包括64位至32位模式转换，中断，异常，陷阱，虚拟化模式传输，系统管理模式传输和/或安全执行模式传输。

公开(公告)号：US09052890B2

公开(公告)日：2015-06-09

申请号：US12924311

申请日：2010-09-25

Applicant: James E. Phillips ,  Kameswar Subramaniam

Inventor： James E. Phillips ,  Kameswar Subramaniam

IPC: G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC classification number: G06F9/30087 ,  G06F9/3842 ,  G06F9/3857

Abstract: An apparatus including an execution logic that includes circuitry to execute instructions, and an instruction execution scheduler logic coupled with the execution logic. The instruction execution scheduler logic is to receive an execute at commit state update instruction. The instruction execution scheduler logic includes at commit state update logic that is to wait to schedule the execute at commit state update instruction for execution until the execute at commit state update instruction is a next instruction to commit. Other apparatus, methods, and systems are also disclosed.

Abstract translation: 一种包括执行逻辑的装置，包括执行指令的电路以及与执行逻辑耦合的指令执行调度器逻辑。 指令执行调度器逻辑是在提交状态更新指令下接收执行。 指令执行调度器逻辑包括提交状态更新逻辑，等待在提交状态更新指令执行执行，直到执行提交状态更新指令是下一个提交指令。 还公开了其他装置，方法和系统。

公开(公告)号：US20160364308A1

公开(公告)日：2016-12-15

申请号：US14737768

申请日：2015-06-12

Applicant: Vedvyas Shanbhogue ,  Eric Rasmussen ,  Deep K. Buch ,  Gordon McFadden ,  Kameswar Subramaniam ,  Amy L. Santoni ,  Willard M. Wiseman ,  Bret L. Toll

Inventor： Vedvyas Shanbhogue ,  Eric Rasmussen ,  Deep K. Buch ,  Gordon McFadden ,  Kameswar Subramaniam ,  Amy L. Santoni ,  Willard M. Wiseman ,  Bret L. Toll

IPC: G06F11/263 ,  G06F11/22

CPC classification number: G06F11/2635 ,  G06F11/1417 ,  G06F11/1433 ,  G06F11/2242 ,  G06F11/2268 ,  G06F11/27

Abstract: In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括至少一个核心，功率管理单元，其具有第一测试寄存器，该第一测试寄存器包括第一字段以存储与测试补丁相关联的测试补丁标识符，以及第二字段以存储测试模式指示符以请求核心 功能测试，以及微代码存储器，用于存储由所述至少一个核执行的微代码。 响应于测试补丁标识符，微代码可以根据从固件接口表获得的地址从非易失性存储器访问固件接口表并获得测试补丁。 描述和要求保护其他实施例。

公开(公告)号：US20140365754A1

公开(公告)日：2014-12-11

申请号：US13915227

申请日：2013-06-11

Applicant: Jonathan D. Combs ,  Kameswar Subramaniam ,  Jeffrey G. Wiedemeier

Inventor： Jonathan D. Combs ,  Kameswar Subramaniam ,  Jeffrey G. Wiedemeier

IPC: G06F9/30

CPC classification number: G06F9/30054 ,  G06F9/30101 ,  G06F9/384

Abstract: A processor includes a microcode storage to store a first microcode subroutine and a microcode caller of the first microcode subroutine. The processor further includes a first microcode alias storage comprising a first plurality of microcode alias locations and a second microcode alias storage comprising a second plurality of microcode alias locations. The processor further includes a first logic, coupled to the first microcode alias storage and to the second microcode alias storage, wherein the first logic is configured to select a first one of a) the first microcode alias storage for storage of a parameter location in one of the first plurality of microcode alias locations or b) the second microcode alias storage for storage of the parameter location in one of the second plurality of microcode alias locations.

Abstract translation: 处理器包括微代码存储器，用于存储第一微代码子程序和第一微代码子程序的微代码调用程序。 处理器还包括包括第一多个微代码别名位置的第一微代码别名存储器和包括第二多个微代码别名位置的第二微码别名存储器。 处理器还包括耦合到第一微代码存储器和第二微代码别名存储器的第一逻辑，其中第一逻辑被配置为选择第一微代码别名存储器中的第一逻辑，用于存储一个参数位置 或b）第二微代码别名存储器，用于存储第二多个微码别名位置之一中的参数位置。

公开(公告)号：US08832419B2

公开(公告)日：2014-09-09

申请号：US12978471

申请日：2010-12-24

Applicant: Jonathan D. Combs ,  Kameswar Subramaniam

Inventor： Jonathan D. Combs ,  Kameswar Subramaniam

IPC: G06F9/28 ,  G06F9/30

CPC classification number: G06F9/28 ,  G06F9/26 ,  G06F9/262 ,  G06F9/30

Abstract: Methods and apparatus for enhanced microcode address stack pointer manipulation are described. In some examples, the stacks are invisible to software. A microcode instruction pointer (UIP) and a next address to be accessed in a microcode storage unit may be generated based on an opcode of a microoperation, a marker, and a UIP stack address. The UIP stack address may be generated based on a signal and an immediate field of the microoperation.

Abstract translation: 描述了用于增强的微代码地址堆栈指针操纵的方法和装置。 在一些示例中，堆栈对于软件是不可见的。 可以基于微操作的操作码，标记和UIP堆栈地址来生成微码指令指针（UIP）和要在微代码存储单元中访问的下一个地址。 可以基于微操作的信号和立即字段来生成UIP堆栈地址。

公开(公告)号：US09329865B2

公开(公告)日：2016-05-03

申请号：US13915227

申请日：2013-06-11

Applicant: Jonathan D. Combs ,  Kameswar Subramaniam ,  Jeffrey G. Wiedemeier

Inventor： Jonathan D. Combs ,  Kameswar Subramaniam ,  Jeffrey G. Wiedemeier

IPC: G06F21/74 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30054 ,  G06F9/30101 ,  G06F9/384

Abstract: A processor includes a microcode storage to store a first microcode subroutine and a microcode caller of the first microcode subroutine. The processor further includes a first microcode alias storage comprising a first plurality of microcode alias locations and a second microcode alias storage comprising a second plurality of microcode alias locations. The processor further includes a first logic, coupled to the first microcode alias storage and to the second microcode alias storage, wherein the first logic is configured to select a first one of a) the first microcode alias storage for storage of a parameter location in one of the first plurality of microcode alias locations or b) the second microcode alias storage for storage of the parameter location in one of the second plurality of microcode alias locations.

Abstract translation: 处理器包括微代码存储器，用于存储第一微代码子程序和第一微代码子程序的微代码调用程序。 处理器还包括包括第一多个微代码别名位置的第一微代码别名存储器和包括第二多个微代码别名位置的第二微码别名存储器。 处理器还包括耦合到第一微代码存储器和第二微代码别名存储器的第一逻辑，其中第一逻辑被配置为选择第一微代码别名存储器中的第一逻辑，用于存储一个参数位置 或b）第二微代码别名存储器，用于存储第二多个微码别名位置之一中的参数位置。