公开(公告)号：US20230393516A1

公开(公告)日：2023-12-07

申请号：US18250100

申请日：2021-11-10

Applicant: Kenichi WATANABE

Inventor： Kenichi WATANABE

IPC: G03G15/00 ,  H05K1/02 ,  H10N10/13 ,  H10N10/82

CPC classification number: G03G15/80 ,  H05K1/0203 ,  H10N10/13 ,  H10N10/82 ,  H05K2201/10219

Abstract: To provide a control board for efficiently generating electric energy in a power generating device from heat generated from an electronic device. A control board includes a board including a first heat dissipating pad; an electronic device including a second heat dissipating pad to dissipate heat; a power generating device including a Peltier device which converts heat energy generated from the electronic device into electric energy, wherein the power generating device is sandwiched between the first heat dissipating pad and the second heat dissipating pad; and a power supply circuit configured to reuse the electric energy.

公开(公告)号：US20190289156A1

公开(公告)日：2019-09-19

申请号：US16299707

申请日：2019-03-12

Applicant: Kenichi Watanabe ,  Tomohiro Shuta ,  Yuuya Mori

Inventor： Kenichi Watanabe ,  Tomohiro Shuta ,  Yuuya Mori

IPC: H04N1/00 ,  G06F1/26

Abstract: A power supply device installed in an electronic apparatus includes a first power supply outputting power upon a plug being connected to a system power supply, a second power supply outputting power upon receiving of a power supply control signal, a third power supply outputting power from a battery, a controller operating using the power from the second power supply and configured to control the electronic apparatus, a flip-flop configured to operate using the power from the third power supply and configured to store, upon activating the electronic apparatus, first logic data or upon shutting down the electronic apparatus, second logic data, and a power supply control switch operating using the power from the first power supply, to output the power supply control signal to the second power supply, in response to activating the electronic apparatus or in response to storing the first logic data in the flip-flop.

公开(公告)号：US09639373B2

公开(公告)日：2017-05-02

申请号：US14806714

申请日：2015-07-23

Applicant: Kenichi Watanabe

Inventor： Kenichi Watanabe

IPC: G06F9/00 ,  G06F9/24 ,  G06F13/00 ,  G06F9/44 ,  G06F9/445

CPC classification number: G06F9/4401 ,  G06F8/65 ,  G06F9/445

Abstract: An information processing apparatus providing a specific function includes a non-volatile function program memory that stores a function program for providing the specific function, a main memory, and an arithmetic device that reads and stores the function program from the function program memory into the main memory at startup of the information processing apparatus and performs an arithmetic operation based on the function program to execute the function program. The arithmetic device operates at a start frequency set for startup as a clock frequency for accessing the function program memory when reading and storing the function program from the function program memory into the main memory at the startup, and operates at a frequency lower than the start frequency as the clock frequency for accessing the function program memory after reading and storing the function program into the main memory.

公开(公告)号：US20160077839A1

公开(公告)日：2016-03-17

申请号：US14806714

申请日：2015-07-23

Applicant: Kenichi WATANABE

Inventor： Kenichi WATANABE

IPC: G06F9/44

CPC classification number: G06F9/4401 ,  G06F8/65 ,  G06F9/445

Abstract: An information processing apparatus providing a specific function includes a non-volatile function program memory that stores a function program for providing the specific function, a main memory, and an arithmetic device that reads and stores the function program from the function program memory into the main memory at startup of the information processing apparatus and performs an arithmetic operation based on the function program to execute the function program. The arithmetic device operates at a start frequency set for startup as a clock frequency for accessing the function program memory when reading and storing the function program from the function program memory into the main memory at the startup, and operates at a frequency lower than the start frequency as the clock frequency for accessing the function program memory after reading and storing the function program into the main memory.

Abstract translation: 提供特定功能的信息处理设备包括存储用于提供特定功能的功能程序的非易失性功能程序存储器，主存储器和运算器件，其将功能程序从功能程序存储器读取并存储到主程序 在信息处理装置启动时的存储器，并且基于该功能程序执行算术运算以执行该功能程序。 当启动时，将功能程序存储器中的功能程序从功能程序存储器读入并存储到主存储器中时，算术装置以设定启动的起始频率作为时钟频率进行操作，并且以低于起动频率 频率作为用于在将功能程序存储到主存储器中之后访问功能程序存储器的时钟频率。

公开(公告)号：US09165881B2

公开(公告)日：2015-10-20

申请号：US13495001

申请日：2012-06-13

Applicant: Kenichi Watanabe

Inventor： Kenichi Watanabe

IPC: H01L29/94 ,  H01L27/108 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A first capacitor recess and a wiring trench are formed through an interlayer insulating film. A lower electrode fills the first capacitor recess, and a first wiring fills the wiring trench. An etching stopper film and a via layer insulating film are disposed over the interlayer insulating film. A first via hole extends through the via layer insulating film and etching stopper film and reaches the first wiring, and a first plug fills the first via hole. A second capacitor recess is formed through the via layer insulating film, the second capacitor recess at least partially overlapping the lower electrode, as viewed in plan. The upper electrode covers the bottom and side surfaces of the second capacitor recess. A capacitor is constituted of the upper electrode, etching stopper film and lower electrode. A second wring connected to the first plug is formed over the via layer insulating film.

Abstract translation: 通过层间绝缘膜形成第一电容器凹部和布线沟槽。 下部电极填充第一电容器凹部，并且第一布线填充布线沟槽。 蚀刻停止膜和通孔层绝缘膜设置在层间绝缘膜上。 第一通孔延伸穿过通孔层绝缘膜和蚀刻阻挡膜并到达第一布线，并且第一插头填充第一通孔。 通过通孔层绝缘膜形成第二电容器凹部，第二电容器凹部至少部分地与下电极重叠，如图所示。 上电极覆盖第二电容器凹部的底表面和侧表面。 电容器由上电极，蚀刻停止膜和下电极构成。 连接到第一插头的第二连接件形成在通孔层绝缘膜上。

公开(公告)号：US09099464B2

公开(公告)日：2015-08-04

申请号：US13330630

申请日：2011-12-19

Applicant: Kenichi Watanabe

Inventor： Kenichi Watanabe

IPC: H01L29/00 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A first capacitor recess and a wiring trench are formed through an interlayer insulating film. A lower electrode fills the first capacitor recess, and a first wiring fills the wiring trench. An etching stopper film and a via layer insulating film are disposed over the interlayer insulating film. A first via hole extends through the via layer insulating film and etching stopper film and reaches the first wiring, and a first plug fills the first via hole. A second capacitor recess is formed through the via layer insulating film, the second capacitor recess at least partially overlapping the lower electrode, as viewed in plan. The upper electrode covers the bottom and side surfaces of the second capacitor recess. A capacitor is constituted of the upper electrode, etching stopper film and lower electrode. A second wring connected to the first plug is formed over the via layer insulating film.

公开(公告)号：US08759192B2

公开(公告)日：2014-06-24

申请号：US13613961

申请日：2012-09-13

Applicant: Kenichi Watanabe

Inventor： Kenichi Watanabe

IPC: H01L21/02 ,  H01L23/522

CPC classification number: H01L23/5223 ,  H01L21/76808 ,  H01L21/76834 ,  H01L23/53238 ,  H01L23/53295 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wiring trench is formed in an interlayer insulating film partway in the depth direction of the interlayer insulating film. A via hole is formed extending from the bottom of the wiring trench to the bottom of the interlayer insulating film. A capacitor recess is formed reaching the bottom of the interlayer insulating film. A conductive member is embedded in the wiring trench and via hole. A capacitor is embedded in the capacitor recess, including a lower electrode, a capacitor dielectric film and an upper electrode. The lower electrode is made of the same material as that of the conductive member and disposed along the bottom and side surface of the capacitor recess. A concave portion is formed on an upper surface of the lower electrode, and the capacitor dielectric film covers an inner surface of the concave portion. The upper electrode is embedded in the concave portion.

Abstract translation: 在层间绝缘膜的深度方向上的中间绝缘膜中形成布线沟槽。 形成从布线沟槽的底部到层间绝缘膜的底部延伸的通孔。 形成电容器凹部到达层间绝缘膜的底部。 导电构件嵌入布线沟槽和通孔中。 电容器嵌入在电容器凹部中，包括下电极，电容器电介质膜和上电极。 下电极由与导电部件相同的材料制成，并沿着电容器凹部的底面和侧面设置。 在下电极的上表面上形成凹部，电容电介质膜覆盖凹部的内表面。 上部电极嵌入凹部。

公开(公告)号：US08709193B2

公开(公告)日：2014-04-29

申请号：US12511180

申请日：2009-07-29

Applicant: Kenichirou Tada ,  Satoru Nakanishi ,  Taku Yamaga ,  Shun Ito ,  Kenichi Watanabe ,  Miyoshi Yokura ,  Masashi Kato ,  Hisashi Katsumata

Inventor： Kenichirou Tada ,  Satoru Nakanishi ,  Taku Yamaga ,  Shun Ito ,  Kenichi Watanabe ,  Miyoshi Yokura ,  Masashi Kato ,  Hisashi Katsumata

IPC: B32B37/00

CPC classification number: B32B38/0008 ,  B32B27/10 ,  B32B27/16 ,  B32B27/286 ,  B32B37/10 ,  B32B37/1054 ,  B32B2037/0092 ,  B32B2262/0269 ,  B32B2262/14 ,  B32B2305/076 ,  B32B2307/206 ,  B32B2307/208 ,  B32B2309/02 ,  B32B2309/105 ,  B32B2309/12 ,  B32B2309/72 ,  B32B2317/12 ,  B32B2367/00 ,  B32B2605/00 ,  H01B3/301 ,  Y10T428/31725

Abstract: A low-temperature plasma treatment is applied to a surface of an aramid paper so as to allow the surface to have a compositional atomic ratio X (O/C) of the number of oxygen atoms (O) to the number of carbon atoms (C) ranging from 110% to 220% of a theoretical atomic ratio. The treatment is performed at an intensity ranging from 120 to 1500 W·min/m2 with a low-temperature plasma treatment apparatus of internal electrode system. The aramid paper is superposed with a nonhydrolyzable resin film and the resulting article is pressurized to give an aramid-resin film laminate. The laminate is inexpensive, has both superior electrical properties and high mechanical strength, excels in elasticity, and is useful as an insulation material.

Abstract translation: 将低温等离子体处理施加到芳族聚酰胺纸的表面，以使表面具有氧原子数（O）与碳原子数（C）的组成原子比X（O / C） ）为理论原子比的110％至220％。 用内部电极系统的低温等离子体处理装置，以120〜1500W·min / m 2的强度进行处理。 将芳族聚酰胺纸与不可水解的树脂膜重叠，并将所得制品加压，得到芳族聚酰胺树脂膜层压体。 该层压板是廉价的，具有优异的电性能和高机械强度，弹性优异，并且可用作绝缘材料。

公开(公告)号：US20130272819A1

公开(公告)日：2013-10-17

申请号：US13773752

申请日：2013-02-22

Applicant: Kuniaki KIMURA ,  Kenichi WATANABE

Inventor： Kuniaki KIMURA ,  Kenichi WATANABE

IPC: B42B5/10

CPC classification number: B42B5/103

Abstract: A bookbinding apparatus inserts ring parts of a comb-shaped ring into binding holes of a sheet bundle and files and binds the sheet bundle, sequentially and includes a binding hole forming section configured to form binding holes in the sheet, a compiling section configured to arrange the sheet in which the binding holes are formed to make the sheet bundle, a comb-shaped ring feeding section configured to feed the comb-shaped ring piece by piece, a binding section configured to receive the fed comb-shaped ring, insert the ring parts of the comb-shaped ring into the binding holes of the sheet bundle, and bind the sheet bundle, and a bound-book discharging section configured to transfer the sheet bundle bound by the binding section to a storage stacker.

Abstract translation: 装订装置将梳形环的环形部件插入片材捆的装订孔中并依次进行文件捆绑并捆扎，并且包括装配孔形成部分，其构造成在片材中形成装订孔;编制部分， 其中装订孔形成以制成片材摞的片材，被配置为一体地供给梳状环件的梳形环供给部分，构造成接收进给的梳形环的装订部分，将环 梳形环的一部分插入片材束的装订孔中，并捆扎片材束，以及装订物排出部分，被配置为将由装订部分束缚的片材束传送到存放堆垛机。

公开(公告)号：US08524568B2

公开(公告)日：2013-09-03

申请号：US13495000

申请日：2012-06-13

Applicant: Kenichi Watanabe

Inventor： Kenichi Watanabe

IPC: H01L21/20

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A first capacitor recess and a wiring trench are formed through an interlayer insulating film. A lower electrode fills the first capacitor recess, and a first wiring fills the wiring trench. An etching stopper film and a via layer insulating film are disposed over the interlayer insulating film. A first via hole extends through the via layer insulating film and etching stopper film and reaches the first wiring, and a first plug fills the first via hole. A second capacitor recess is formed through the via layer insulating film, the second capacitor recess at least partially overlapping the lower electrode, as viewed in plan. The upper electrode covers the bottom and side surfaces of the second capacitor recess. A capacitor is constituted of the upper electrode, etching stopper film and lower electrode. A second wring connected to the first plug is formed over the via layer insulating film.