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    VIA STUB ELIMINATION
    1.
    发明申请
    VIA STUB ELIMINATION 审中-公开
    通过立场消除

    公开(公告)号：US20120211273A1

    公开(公告)日：2012-08-23

    申请号：US13417023

    申请日：2012-03-09

    Applicant: Joseph Kuczynski ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil ,  Paul Alan Vermilyea

    Inventor： Joseph Kuczynski ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil ,  Paul Alan Vermilyea

    IPC: H05K1/11 ,  H05K3/00

    CPC classification number: H05K3/429 ,  B33Y80/00 ,  H05K1/0237 ,  H05K1/115 ,  H05K3/0082 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/09645 ,  H05K2203/056 ,  H05K2203/0565 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: An enhanced mechanism is disclosed for via stub elimination in printed wiring boards (PWBs) and other substrates. In one embodiment, the substrate includes a plurality of insulator layers and internal conductive traces. First and second through-holes extend completely through the substrate and respectively pass through first and second ones of the internal conductive traces, which are at different depths within the substrate. Photolithographic techniques are used to generate plated-through-hole (PTH) plugs of controlled, variable depth in the through-holes before first and second conductive vias are respectively plated onto the first and second through-holes. The depth of these PTH plugs is controlled (e.g., using a photomask and/or variable laser power) to prevent the first and second conductive vias from extending substantially beyond the first and second internal conductive traces, respectively, and thereby prevent via stubs from being formed in the first place.

    Abstract translation: 公开了用于印刷电路板（PWB）和其它基板中的通孔短截线的增强机构。 在一个实施例中，衬底包括多个绝缘体层和内部导电迹线。 第一和第二通孔完全延伸穿过衬底并且分别穿过在衬底内的不同深度的第一和第二内部导电迹线。 光刻技术用于在将第一和第二导电通孔分别电镀到第一和第二通孔之前，在通孔中产生受控的可变深度的电镀通孔（PTH）插头。 控制这些PTH插头的深度（例如，使用光掩模和/或可变激光功率）来防止第一和第二导电通孔分别基本上延伸超出第一和第二内部导电迹线，从而防止通孔短路 形成在第一位。

    Horizontally Split Vias
    2.
    发明申请
    Horizontally Split Vias 有权
    水平分流通风口

    公开(公告)号：US20100044096A1

    公开(公告)日：2010-02-25

    申请号：US12193842

    申请日：2008-08-19

    Applicant: Joseph Kuczynski ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil ,  Paul Alan Vermilyea

    Inventor： Joseph Kuczynski ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil ,  Paul Alan Vermilyea

    IPC: H05K1/11 ,  B05D5/12 ,  B05D3/00

    CPC classification number: H05K3/429 ,  B33Y30/00 ,  B33Y80/00 ,  H05K1/115 ,  H05K3/0082 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2203/056 ,  H05K2203/0565 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

    Abstract: A mechanism is disclosed for providing horizontally split vias are provided in printed wiring boards (PWBs) and other substrates. In one embodiment, the substrate includes a plurality of insulator layers and internal conductive traces. First and second through-holes extend completely through the substrate and respectively pass through first/second ones and third/fourth ones of the internal conductive traces, which are at different depths within the substrate. Photolithographic techniques are used to generate plated-through-hole (PTH) plugs of controlled, variable depth in the through-holes before first/second conductive vias are plated onto the first through-hole and before third/fourth conductive vias are plated onto the second through-hole. The depth of these PTH plugs is controlled (e.g., using a photomask and/or variable laser power) to prevent the conductive vias from extending substantially beyond their respective internal conductive traces, thereby horizontally spitting the two conductive vias plated onto each of the through-holes. This advantageously increases wiring density up to 2×.

    Abstract translation: 公开了一种用于在印刷电路板（PWB）和其它基板中提供水平分割通孔的机构。 在一个实施例中，衬底包括多个绝缘体层和内部导电迹线。 第一和第二通孔完全延伸穿过衬底并且分别穿过在衬底内的不同深度的内部导电迹线的第一/第二和第三/第四通孔。 光刻技术用于在将第一/第二导电通孔电镀到第一通孔上之前并且在将第三/第四导电通孔电镀到第一通孔之前，在通孔中产生受控的可变深度的电镀通孔（PTH）插头 第二通孔。 控制这些PTH插头的深度（例如，使用光掩模和/或可变激光功率）来防止导电通孔基本上延伸超过它们各自的内部导电迹线，从而水平地喷射镀在每个通孔上的两个导电通孔， 孔。 这有利地将布线密度提高到2×。

    Method and system for alignment of graphite nanofibers for enhanced thermal interface material performance
    4.
    发明授权
    Method and system for alignment of graphite nanofibers for enhanced thermal interface material performance 有权
    用于石墨纳米纤维对准的方法和系统，用于增强热界面材料性能

    公开(公告)号：US08431048B2

    公开(公告)日：2013-04-30

    申请号：US12842200

    申请日：2010-07-23

    Applicant: Joseph Kuczynski ,  Arvind Kumar Sinha ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil

    Inventor： Joseph Kuczynski ,  Arvind Kumar Sinha ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil

    IPC: H05K7/20

    CPC classification number: B82Y40/00 ,  B82Y30/00 ,  C01B32/15 ,  C01B32/20 ,  H01L23/373 ,  H01L23/3733 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The exemplary embodiments of the present invention provide a method and system for aligning graphite nanofibers in a thermal interface material to enhance the thermal interface material performance. The method includes preparing the graphite nanofibers in a herringbone configuration, and dispersing the graphite nanofibers in the herringbone configuration into the thermal interface material. The method further includes applying a magnetic field of sufficient intensity to align the graphite nanofibers in the thermal interface material. The system includes the graphite nanofibers configured in a herringbone configuration and a means for dispersing the graphite nanofibers in the herringbone configuration into the thermal interface material. The system further includes a means for applying a magnetic field of sufficient intensity to align the graphite nanofibers in the thermal interface material.

    Abstract translation: 本发明的示例性实施例提供了一种用于在石墨纳米纤维中对准热界面材料以提高热界面材料性能的方法和系统。 该方法包括以人字形配置制备石墨纳米纤维，并将石英纳米纤维以人字形构型分散到热界面材料中。 该方法还包括施加足够强度的磁场以使石墨纳米纤维在热界面材料中对准。 该系统包括以人字形配置的石墨纳米纤维和用于将人字形配置中的石墨纳米纤维分散到热界面材料中的装置。 该系统还包括用于施加足够强度的磁场以对准热界面材料中的石墨纳米纤维的装置。

    Electrical connector with elastomeric pad having compressor fingers each including a filler member to mitigate relaxation of the elastomer
    5.
    发明授权
    Electrical connector with elastomeric pad having compressor fingers each including a filler member to mitigate relaxation of the elastomer 失效
    具有弹性体垫的电连接器，其具有压缩机指状件，每个包括填充构件以减轻弹性体的松弛

    公开(公告)号：US06991473B1

    公开(公告)日：2006-01-31

    申请号：US11000453

    申请日：2004-11-30

    Applicant: Gregory Ervin Balcome ,  Joseph Kuczynski ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil ,  Paul Alan Vermilyea

    Inventor： Gregory Ervin Balcome ,  Joseph Kuczynski ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil ,  Paul Alan Vermilyea

    IPC: H01R12/00 ,  H05K1/00

    CPC classification number: H01R12/62 ,  H01R13/24 ,  H01R13/6215 ,  H05K3/365 ,  H05K2201/10393

    Abstract: An electrical connector includes connector pads on a printed circuit board and contact members on an insulating substrate. The contact members are pressed against the contact pads by a compression mat having compressor fingers. A clamping arrangement forces the compressor fingers against the substrate and thereby presses the contact members against the contact pads. To counteract the inherent tendency of the compressor fingers to undergo stress relaxation after the compressor mat has been clamped, the connector also includes filler members disposed at least partially within the compressor fingers, essentially a “button-within-a-button” arrangement. Optionally, a filler deflection member may be interposed between the compression mat and a clamping plate of the clamping arrangement so that the filler deflection member abuts against the filler members. Alternatively, the filler members may be integral features of the deflection member.

    Abstract translation: 电连接器包括印刷电路板上的连接器焊盘和绝缘基板上的接触部件。 接触构件通过具有压缩指状物的压缩垫压靠在接触垫上。 夹紧装置迫使压缩机手指抵靠基板，从而将接触构件压靠在接触垫上。 为了抵消在压缩机垫被夹紧之后压缩机手指经受应力松弛的固有趋势，连接器还包括至少部分地设置在压缩机指状件内的填充构件，基本上是“按钮内按钮”结构。 可选地，填料偏转构件可插入在压缩垫和夹紧装置的夹紧板之间，使得填料偏转构件抵靠填料构件。 或者，填充构件可以是偏转构件的整体特征。

    SEM sample holder apparatus for implementing enhanced examination of multiple samples
    6.
    发明授权
    SEM sample holder apparatus for implementing enhanced examination of multiple samples 失效
    用于实施多个样品的增强检查的SEM样品架设备

    公开(公告)号：US06872955B1

    公开(公告)日：2005-03-29

    申请号：US10728298

    申请日：2003-12-04

    Applicant: Gregory Ervin Balcome ,  Kevin Albert Splittstoesser

    Inventor： Gregory Ervin Balcome ,  Kevin Albert Splittstoesser

    IPC: H01J37/04

    CPC classification number: H01J37/20 ,  H01J2237/201

    Abstract: A method and a scanning electron microscope (SEM) holder apparatus are provided for implementing examination of multiple samples. The SEM holder apparatus includes a metal plate. The metal plate includes a plurality of through holes arranged in a predefined pattern, a mounting opening, and an O-ring receiving recess extending within the metal plate to the plurality of through holes. The SEM holder apparatus includes a plurality of sample holders, each inserted within a selected one of the plurality of through holes. An O-ring is inserted within the O-ring receiving recess to provide a secure mounting of the plurality of sample holders. The O-ring protrudes partially into the through holes receiving the sample holders, providing positive holding pressure that ensures a secure mounting of the sample holders to provide electrical conductivity and vibration suppression.

    Abstract translation: 提供了一种用于实施多个样品检查的方法和扫描电子显微镜（SEM）支架装置。 SEM支架装置包括金属板。 金属板包括以预定图案布置的多个通孔，安装开口和在金属板内延伸到多个通孔的O形环容纳凹部。 SEM支架装置包括多个样本保持器，每个样本保持器插入到多个通孔中的选定的一个中。 O形环插入在O形环容纳凹部内，以提供多个样品架的安全安装。 O形环部分地突出到接收样品保持器的通孔中，提供正的保持压力，确保样品保持器的安全安装以提供导电性和振动抑制。

    Method for via stub elimination
    9.
    发明授权
    Method for via stub elimination 有权
    通过短截线消除的方法

    公开(公告)号：US08230592B2

    公开(公告)日：2012-07-31

    申请号：US12193837

    申请日：2008-08-19

    Applicant: Joseph Kuczynski ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil ,  Paul Alan Vermilyea

    Inventor： Joseph Kuczynski ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil ,  Paul Alan Vermilyea

    IPC: H01K3/10

    CPC classification number: H05K3/429 ,  B33Y80/00 ,  H05K1/0237 ,  H05K1/115 ,  H05K3/0082 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/09645 ,  H05K2203/056 ,  H05K2203/0565 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: An enhanced mechanism is disclosed for via stub elimination in printed wiring boards (PWBs) and other substrates. In one embodiment, the substrate includes a plurality of insulator layers and internal conductive traces. First and second through-holes extend completely through the substrate and respectively pass through first and second ones of the internal conductive traces, which are at different depths within the substrate. Photolithographic techniques are used to generate plated-through-hole (PTH) plugs of controlled, variable depth in the through-holes before first and second conductive vias are respectively plated onto the first and second through-holes. The depth of these PTH plugs is controlled (e.g., using a photomask and/or variable laser power) to prevent the first and second conductive vias from extending substantially beyond the first and second internal conductive traces, respectively, and thereby prevent via stubs from being formed in the first place. This advantageously eliminates the costly and time consuming process of via stub backdrilling.

    Abstract translation: 公开了用于印刷电路板（PWB）和其它基板中的通孔短截线的增强机构。 在一个实施例中，衬底包括多个绝缘体层和内部导电迹线。 第一和第二通孔完全延伸穿过衬底并且分别穿过在衬底内的不同深度的第一和第二内部导电迹线。 光刻技术用于在将第一和第二导电通孔分别电镀到第一和第二通孔之前，在通孔中产生受控的可变深度的电镀通孔（PTH）插头。 控制这些PTH插头的深度（例如，使用光掩模和/或可变激光功率）来防止第一和第二导电通孔分别基本上延伸超出第一和第二内部导电迹线，从而防止通孔短路 形成在第一位。 这有利地消除了通过短管回钻的昂贵且耗时的过程。

    Method of forming a substrate having a plurality of insulator layers
    10.
    发明授权
    Method of forming a substrate having a plurality of insulator layers 有权
    形成具有多个绝缘体层的衬底的方法

    公开(公告)号：US08136240B2

    公开(公告)日：2012-03-20

    申请号：US12193842

    申请日：2008-08-19

    Applicant: Joseph Kuczynski ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil ,  Paul Alan Vermilyea

    Inventor： Joseph Kuczynski ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil ,  Paul Alan Vermilyea

    IPC: H01K3/00

    CPC classification number: H05K3/429 ,  B33Y30/00 ,  B33Y80/00 ,  H05K1/115 ,  H05K3/0082 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2203/056 ,  H05K2203/0565 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

    Abstract: A mechanism is disclosed for providing horizontally split vias in printed wiring boards (PWBs) and other substrates. In one embodiment, the substrate includes a plurality of insulator layers and internal conductive traces. First and second through-holes extend completely through the substrate and respectively pass through first/second ones and third/fourth ones of the internal conductive traces, which are at different depths within the substrate. Photolithographic techniques are used to generate plated-through-hole (PTH) plugs of controlled, variable depth in the through-holes before first/second conductive vias are plated onto the first through-hole and before third/fourth conductive vias are plated onto the second through-hole. The depth of these PTH plugs is controlled (e.g., using a photomask and/or variable laser power) to prevent the conductive vias from extending substantially beyond their respective internal conductive traces, thereby horizontally spitting the two conductive vias plated onto each of the through-holes. This advantageously increases wiring density up to 2×.

    Abstract translation: 公开了用于在印刷电路板（PWB）和其它基板中提供水平分开的通孔的机构。 在一个实施例中，衬底包括多个绝缘体层和内部导电迹线。 第一和第二通孔完全延伸穿过衬底并且分别穿过在衬底内的不同深度的内部导电迹线的第一/第二和第三/第四通孔。 光刻技术用于在将第一/第二导电通孔电镀到第一通孔上之前并且在将第三/第四导电通孔电镀到第一通孔之前，在通孔中产生受控的可变深度的电镀通孔（PTH）插头 第二通孔。 控制这些PTH插头的深度（例如，使用光掩模和/或可变激光功率）来防止导电通孔基本上延伸超过它们各自的内部导电迹线，从而水平地喷射镀在每个通孔上的两个导电通孔， 孔。 这有利地将布线密度提高到2×。

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