公开(公告)号：US08830725B2

公开(公告)日：2014-09-09

申请号：US13209569

申请日：2011-08-15

Applicant: Donald S Bethune ,  Kailash Gopalakrishnan ,  Andrew J Kellock ,  Rohit S Shenoy ,  Kumar R Virwani

Inventor： Donald S Bethune ,  Kailash Gopalakrishnan ,  Andrew J Kellock ,  Rohit S Shenoy ,  Kumar R Virwani

IPC: G11C11/00

CPC classification number: H01L29/872 ,  G11C13/003 ,  G11C2029/5002 ,  G11C2029/5006 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/224 ,  H01L27/2427 ,  H01L45/141 ,  H01L45/1616

Abstract: A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.

Abstract translation: 夹在两个导电电极之间的晶体半导体肖特基势垒状二极管与存储元件，字线和位线串联，其中，该设置提供大于1V的电压裕度和大于5×106A / cm 2的电流密度。 这种肖特基势垒状二极管可以在与低温BEOL半导体处理兼容的条件下制造，可以在低电压下提供高电流，具有高开关比，并且可以实现大型存储器阵列。

公开(公告)号：US20080257867A1

公开(公告)日：2008-10-23

申请号：US11661474

申请日：2005-08-26

Applicant: Ajay P Malshe ,  Kumar R. Virwani ,  Kalmakar P. Rajurkar

Inventor： Ajay P Malshe ,  Kumar R. Virwani ,  Kalmakar P. Rajurkar

IPC: H01L21/00

CPC classification number: B81C1/00492 ,  B81C2201/0145 ,  G01Q80/00

Abstract: An apparatus for nano-scale electric discharge machining of a conductive workpiece. In one embodiment, the apparatus includes a dielectric medium deposited on a surface of the workpiece to form a dielectric layer having a thickness, a positioning device capable of moving in three dimensions, an electrode having a nano-scaled tip and mounted to the positioning device, a power source electrically coupled with the electrode and the workpiece, and a controller in communication with the positioning device for generating a signal to cause the nano-scaled tip of the electrode to move to a desired position over the surface of the workpiece. In operation a biasing voltage over a threshold voltage is applied from the power source between the nano-scaled tip of the electrode and the surface of the workpiece such that an avalanche current is formed across the nano-scaled tip of the electrode and the surface of the workpiece to perform machining of the workpiece.

Abstract translation: 一种用于导电工件的纳米级放电加工的装置。 在一个实施例中，该装置包括沉积在工件的表面上以形成具有厚度的电介质层的电介质介质层，能够三维移动的定位装置，具有纳米级尖端的电极并安装到定位装置 与电极和工件电耦合的电源，以及与定位装置连通的控制器，用于产生信号以使电极的纳米级尖端移动到工件表面上的期望位置。 在操作中，从电源在电极的纳米级尖端和工件表面之间施加超过阈值电压的偏置电压，使得在电极的纳米级尖端和跨越电极的表面形成雪崩电流 工件对工件进行加工。

公开(公告)号：US20130044532A1

公开(公告)日：2013-02-21

申请号：US13209569

申请日：2011-08-15

Applicant: Donald S. Bethune ,  Kailash Gopalakrishnan ,  Andrew J. Kellock ,  Rohit S. Shenoy ,  Kumar R. Virwani

Inventor： Donald S. Bethune ,  Kailash Gopalakrishnan ,  Andrew J. Kellock ,  Rohit S. Shenoy ,  Kumar R. Virwani

IPC: G11C11/00 ,  H01L45/00

CPC classification number: H01L29/872 ,  G11C13/003 ,  G11C2029/5002 ,  G11C2029/5006 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/224 ,  H01L27/2427 ,  H01L45/141 ,  H01L45/1616

Abstract: A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.

Abstract translation: 夹在两个导电电极之间的晶体半导体肖特基势垒状二极管与存储元件，字线和位线串联，其中，该设置提供大于1V的电压裕度和大于5×106A / cm 2的电流密度。 这种肖特基势垒状二极管可以在与低温BEOL半导体处理兼容的条件下制造，可以在低电压下提供高电流，具有高开关比，并且可以实现大型存储器阵列。