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公开(公告)号:US20250166991A1
公开(公告)日:2025-05-22
申请号:US18840480
申请日:2023-02-10
Applicant: Lam Research Corporation
Inventor: Tong LEI , Yushan CHI , Jiang YU
Abstract: UV light may be directed through a patterned window to cause selective UV exposure of certain areas of a substrate. A stress-tunable film deposited on the substrate may undergo localized stress changes from selective UV exposure. Localized stress changes in the stress-tunable film may mitigate wafer bowing in the substrate. The patterned window may be designed with UV-transparent regions and UV-non-transparent regions to facilitate targeted UV exposure of the stress-tunable film. In some implementations, the patterned window may include a metal coating, a ceramic cover, or a metal cover for selective UV exposure. In some implementations, the patterned window may further include transition regions that permit partial transmission of UV light to limit stress changes in corresponding areas of the stress-tunable film.
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公开(公告)号:US20250164526A1
公开(公告)日:2025-05-22
申请号:US18695091
申请日:2022-09-26
Applicant: LAM RESEARCH CORPORATION
Inventor: John PEASE , Thomas W. ANDERSON , Michael DRYMON
Abstract: A probe assembly includes a stepped insulator and a printed circuit board. The insulator is configured to surround a current carrying conductor. The printed circuit board includes a main portion and an outward protruding portion. The outward protruding portion is implemented as a voltage probe and extends outward away from the main portion and into the insulator. The printed circuit board includes a conductive element, one or more dielectric layers, and a pickup element, where the conductive element extends through the one or more dielectric layers and is connected to the pickup element, and where the pickup element is embedded in the one or more dielectric layers and disposed proximate the current carrying conductor. The printed circuit board includes signal conditioning components connected to the conductive element of the voltage probe.
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公开(公告)号:US12302760B2
公开(公告)日:2025-05-13
申请号:US18670641
申请日:2024-05-21
Applicant: Lam Research Corporation
Inventor: Thorsten Lill , Ivan L. Berry, III
Abstract: Patterned magnetoresistive random access memory (MRAM) stacks are formed by performing a main etch through a plurality of MRAM layers disposed on a substrate, where the main etch includes using ion beam etching (IBE). After the main etch, gapfill dielectric material is deposited in spaces between the patterned MRAM stacks, and the gapfill dielectric material is selectively etched or otherwise formed to an etch depth that is above a depth of an underlayer. After the gapfill dielectric material is formed, at least some of the gapfill dielectric material and any electrically conductive materials deposited on sidewalls of the patterned MRAM stacks are removed by performing an IBE trim etch.
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公开(公告)号:US20250149306A1
公开(公告)日:2025-05-08
申请号:US18835982
申请日:2022-12-19
Applicant: Lam Research Corporation
Inventor: Pratik Mankidy , Jaewon Kim
IPC: H01J37/32 , H01L21/67 , H01L21/687
Abstract: An edge ring for use in a plasma chamber includes a first pair of edge ring segments with each one of the first pair of edge ring segments having a first thickness and a second pair of edge ring segments with each one of the second pair of edge ring segments having a second thickness. Each of the first pair of edge ring segments is oriented adjacent to each of the second pair of edge ring segments and each of the second pair of edge ring segments is oriented adjacent to each of the first pair of edge ring segments.
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公开(公告)号:US12293943B2
公开(公告)日:2025-05-06
申请号:US17430617
申请日:2020-02-13
Applicant: Lam Research Corporation
Inventor: Lee Peng Chua , Defu Liang , Jacob Kurtis Blickensderfer , Thomas A Ponnuswamy , Bryan L. Buckalew , Steven T. Mayer
IPC: H01L21/768 , C25D3/48 , C25D5/02 , C25D7/12 , C25D17/06 , H01L21/311 , H01L23/48
Abstract: Systems and methods are provided for method for etch assisted gold (Au) through silicon mask plating (EAG-TSM). An example method comprises providing a seed layer on a substrate and providing a silicon mask on at least a portion of the seed layer on the substrate. The silicon mask includes one or more via to be filled with Au. The masked substrate is subjected to at least one processing cycle, each processing cycle including an Au plating sub-step and an etch treatment sub-step. The cycles are repeated until a selected via fill thickness is achieved.
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公开(公告)号:US12293919B2
公开(公告)日:2025-05-06
申请号:US18505043
申请日:2023-11-08
Applicant: Lam Research Corporation
Inventor: Seongjun Heo , Jengyi Yu , Chen-Wei Liang , Alan J. Jensen , Samantha S. H. Tan
IPC: H01L21/3065 , H01L21/02 , H01L21/033 , H01L21/67
Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl2 and BCl3.
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公开(公告)号:US20250140565A1
公开(公告)日:2025-05-01
申请号:US19011455
申请日:2025-01-06
Applicant: Lam Research Corporation
Inventor: Nikhil Dole , Merrett Tinlok Wong , Eric Hudson , Sangheon Lee , Xiaoqiang Yao
IPC: H01L21/311 , H01J37/32 , H01L21/3065
Abstract: A method for multi-state pulsing to achieve a balance between bow control and mask selectivity is described. The method includes generating a primary radio frequency (RF) signal. The primary RF signal pulses among three states including a first state, a second state, and a third state. The method further includes generating a secondary RF signal. The secondary RF signal pulses among the three states. During the first state, the primary RF signal has a power level that is greater than a power level of the secondary RF signal. Also, during the second state, the secondary RF signal has a power level that is greater than a power level of the primary RF signal. During the third state, power levels of the primary and secondary RF signals are approximately equal.
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公开(公告)号:US20250140529A1
公开(公告)日:2025-05-01
申请号:US18835328
申请日:2022-12-19
Applicant: Lam Research Corporation
Inventor: Andreas Fischer , Gnanamani Amburose , Julien Monbeig
IPC: H01J37/32 , H01L21/683
Abstract: A confinement ring for use in a process chamber includes a tubular extension that is configured to surrounds a process region in the process chamber. An upper end of the tubular extension is configured to connect to a showerhead of the process chamber and a lower end that is configured to extend into the process region and proximate to an edge ring that surrounds a wafer received within the process region. A foot extension has an inner end that joins to the lower end of the tubular extension and extends outwardly from the process region to the outer end. The foot extension provides an annular surface that is configured to form a gap with a top surface of the edge ring.
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公开(公告)号:US20250140528A1
公开(公告)日:2025-05-01
申请号:US18867773
申请日:2023-05-17
Applicant: Lam Research Corporation
Inventor: Jeremiah Michael DEDERICK , Satish SRINIVASAN , Lin XU , John DAUGHERTY
Abstract: A component of a plasma processing chamber is provided. A yttria coating is formed on a surface of a component body, wherein the yttria coating is deposited by aerosol deposition and is annealed, wherein the yttria coating is at least 95% pure yttria by weight.
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公开(公告)号:US12288685B2
公开(公告)日:2025-04-29
申请号:US17045629
申请日:2019-04-08
Applicant: Lam Research Corporation
Inventor: Jeremy D. Fields , Awnish Gupta , Douglas W. Agnew , Joseph R. Abel , Purushottam Kumar
IPC: H01L21/02 , C23C16/455 , G03F7/16 , H01J37/32 , H01L21/027
Abstract: Methods and apparatuses for modifying a wafer surface using an organosilicon precursor are provided herein. The wafer surface is dosed with the organosilicon precursor following deposition of a dielectric material by an atomic layer deposition (ALD) process. In some implementations, the dielectric layer is made of silicon oxide. Dosing the wafer surface with the organosilicon precursor may occur in the same chamber as the ALD process. The organosilicon precursor may modify the wafer surface to increase its hydrophobicity so that photoresist adhesion is improved on the wafer surface. In some implementations, the wafer surface may be exposed to an inert gas RF plasma after dosing the wafer surface with the organosilicon precursor.
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