公开(公告)号：US20120233575A1

公开(公告)日：2012-09-13

申请号：US13044578

申请日：2011-03-10

Applicant: Madhur KASHYAP

Inventor： Madhur KASHYAP

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A layout method for an integrated circuit including vias connecting stacked metal layers through cuts in intermediate cut layers includes generating interconnection blockage and obstruction statements that define exclusion regions of the metal layers blocked by existing initial interconnections for routing additional interconnections. Shape, size and spacing data are generated for de-selection areas of the exclusion regions in the conductive layers. The de-selection areas are sufficiently far from the boundaries of the exclusion regions that cut spacing rules applied to the initial cuts within the de-selection areas do not block placement of additional cuts outside the exclusion regions of the conductive layers. Only those of the initial cuts within the exclusion regions that lie outside the de-selection areas are selected. Cut blockage and obstruction statements are generated for the selected cuts. A layout view is derived, including routing the additional interconnections in the electrically conductive layers and placing the additional cuts.

Abstract translation: 集成电路的布局方法包括通过中间切割层中的切割连接堆叠的金属层的通孔，包括产生互连阻塞和障碍物语句，其定义被现有初始互连阻挡以排除附加互连的金属层的排除区域。 为导电层中的排除区域的去选择区域生成形状，尺寸和间隔数据。 去选择区域离排除区域的边界足够远，所述排除区域的切割间隔规则应用于去选择区域内的初始切割不阻止在导电层的排除区域之外的附加切口的放置。 仅选择位于解除区域之外的排除区域内的初始切割。 为所选切口生成切割阻塞和阻塞声明。 导出布局视图，包括在导电层中布置附加互连并放置附加切口。

公开(公告)号：US20070256042A1

公开(公告)日：2007-11-01

申请号：US11737759

申请日：2007-04-20

Applicant: Madhur Kashyap ,  Arijit Dutta

Inventor： Madhur Kashyap ,  Arijit Dutta

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: A method of conducting timing analysis on an integrated circuit design includes performing a first routing operation on the design to generate a first routed design that includes redundant vias, and storing the first routed design in a first design database, and performing a second routing operation on the synthesized design to generate a second routed design that does not include redundant vias, and storing the second routed design in a second design database. Then, extractions are performed on the first and second designs and delay calculations are performing on the first and second extractions files. The first and second delay calculations are compared to determine a delay difference between the first and second designs and timing analysis is performed using the delay difference.

Abstract translation: 对集成电路设计进行定时分析的方法包括对设计执行第一路由操作以生成包括冗余过孔的第一路由设计，以及将第一路由设计存储在第一设计数据库中，以及执行第二路由操作 合成设计以生成不包括冗余通孔的第二路由设计，以及将第二路由设计存储在第二设计数据库中。 然后，在第一和第二设计上执行提取，并且在第一和第二提取文件上执行延迟计算。 比较第一和第二延迟计算以确定第一和第二设计之间的延迟差异，并且使用延迟差执行定时分析。

公开(公告)号：US08843873B1

公开(公告)日：2014-09-23

申请号：US14100005

申请日：2013-12-08

Applicant: Pramod Sharma ,  Madhur Kashyap ,  Narayanan Kannan

Inventor： Pramod Sharma ,  Madhur Kashyap ,  Narayanan Kannan

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/76

Abstract: A method of estimating capacitive cell load of cells in an integrated circuit (IC) design uses first maximum capacitive load values CMAX—LIB in calculating risk of electromigration failure in cells of the IC design. CMAX—LIB is saved for a cell whose risk of electromigration failure is acceptable. For a failed cell, a revised maximum capacitive load value CMAX—2 is reduced as the ratio of an actual current IACTUAL—1 relative to the electromigration current limit ILIMIT in the weakest element of the cell. A revised actual current IACTUAL—2 is obtained as a function of transition times with CMAX—2. CMAX—2 is saved for the cell if IACTUAL—2 is less than ILIMIT. Otherwise the steps of calculating CMAX—2 and IACTUAL—2 are re-iterated. CMAX—2 is reduced relative to CMAX—LIB for the first iteration and is further reduced relative to its previous value CMAX—2 for subsequent iterations.

Abstract translation: 在集成电路（IC）设计中估计电池的电容单元负载的方法在计算IC设计的单元中的电迁移故障风险时使用第一最大容性负载值CMAX-LIB。 CMAX-LIB被保存用于电迁移失败风险可接受的电池。 对于故障单元，修正的最大容性负载值CMAX-2随着电池最弱元件中实际电流IACTUAL-1与电迁移电流限制ILIMIT的比值而减小。 作为CMAX-2的转换时间的函数，获得修正的实际电流IACTUAL-2。 如果IACTUAL-2小于ILIMIT，则为单元格保存CMAX-2。 否则，重新计算CMAX-2和IACTUAL-2的步骤。 CMAX-2相对于CMAX-LIB相对于第一次迭代而减小，并且相对于其先前的值CMAX-2进一步减小以用于后续迭代。

公开(公告)号：US07673268B2

公开(公告)日：2010-03-02

申请号：US11737759

申请日：2007-04-20

Applicant: Madhur Kashyap ,  Arijit Dutta

Inventor： Madhur Kashyap ,  Arijit Dutta

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: A method of conducting timing analysis on an integrated circuit design includes performing a first routing operation on the design to generate a first routed design that includes redundant vias, and storing the first routed design in a first design database, and performing a second routing operation on the synthesized design to generate a second routed design that does not include redundant vias, and storing the second routed design in a second design database. Then, extractions are performed on the first and second designs and delay calculations are performing on the first and second extractions files. The first and second delay calculations are compared to determine a delay difference between the first and second designs and timing analysis is performed using the delay difference.

Abstract translation: 对集成电路设计进行定时分析的方法包括对设计执行第一路由操作以生成包括冗余过孔的第一路由设计，以及将第一路由设计存储在第一设计数据库中，以及执行第二路由操作 合成设计以生成不包括冗余通孔的第二路由设计，以及将第二路由设计存储在第二设计数据库中。 然后，在第一和第二设计上执行提取，并且在第一和第二提取文件上执行延迟计算。 比较第一和第二延迟计算以确定第一和第二设计之间的延迟差异，并且使用延迟差执行定时分析。