公开(公告)号：US08035218B2

公开(公告)日：2011-10-11

申请号：US12590138

申请日：2009-11-03

Applicant: John S. Guzek ,  Mahadevan Survakumar ,  Hamid R. Azimi

Inventor： John S. Guzek ,  Mahadevan Survakumar ,  Hamid R. Azimi

IPC: H01L23/48 ,  H01L29/40

CPC classification number: H01L23/49833 ,  H01L22/14 ,  H01L22/20 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

公开(公告)号：US20110101516A1

公开(公告)日：2011-05-05

申请号：US12590138

申请日：2009-11-03

Applicant: John S. Guzek ,  Mahadevan Survakumar ,  Hamid R. Azimi

Inventor： John S. Guzek ,  Mahadevan Survakumar ,  Hamid R. Azimi

IPC: H01L23/10 ,  H01L21/00 ,  H01L21/66

CPC classification number: H01L23/49833 ,  H01L22/14 ,  H01L22/20 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

Abstract translation: 微电子封装包括具有第一表面区域（125）的第一衬底（120）和具有第二表面区域（135）的第二衬底（130）。 第一衬底包括在第一表面处具有第一间距（127）的第一组互连（126）和在第二表面（222）处具有第二间距（129）的第二组互连（128）。 第二衬底使用第二组互连件耦合到第一衬底，并且包括具有第三间距（237）和第三组互连（236）的第三组互连（236），并且内部导电层（233,234）以微孔（ 240）。 第一间距小于第二间距，第二间距小于第三间距，第一表面积小于第二表面积。

公开(公告)号：US06936498B2

公开(公告)日：2005-08-30

申请号：US10857391

申请日：2004-05-28

Applicant: Mahadevan Survakumar

Inventor： Mahadevan Survakumar

IPC: H01L23/498 ,  H01L23/50 ,  H05K1/16 ,  H05K3/00 ,  H05K3/46 ,  H01L21/44 ,  H01L21/20

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/00014 ,  H05K1/162 ,  H05K3/0032 ,  H05K3/4644 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09672 ,  H01L2224/0401

Abstract: A package with increased capacitance comprises a core and a plurality of buildup layers. The core has an inner dielectric portion and the core outer conductive layer. The buildup layers are disposed over the core and have offset ablated regions reducing the thickness of the buildup layers in the ablated regions. Conductive material is plated on the buildup layers including within the ablated regions. The reduced thickness and increased plate area due to the ablated regions increases the capacitance between adjacent buildup layers. Processors and processing systems may take advantage of the increased capacitance in the package to draw more current and operate at higher data rates.

Abstract translation: 具有增加电容的封装包括芯和多个堆积层。 芯具有内绝缘部分和芯外导电层。 堆积层设置在芯上并且具有偏移的消融区域以减小烧蚀区域中积聚层的厚度。 导电材料镀在包括烧蚀区域内的积层上。 由于烧蚀区域减小的厚度和增加的板面积增加了相邻堆积层之间的电容。 处理器和处理系统可以利用增加的封装中的电容来绘制更多的电流并以更高的数据速率工作。

公开(公告)号：US06787902B1

公开(公告)日：2004-09-07

申请号：US10401379

申请日：2003-03-27

Applicant: Mahadevan Survakumar

Inventor： Mahadevan Survakumar

IPC: H01L2334

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/00014 ,  H05K1/162 ,  H05K3/0032 ,  H05K3/4644 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09672 ,  H01L2224/0401

Abstract: A package with increased capacitance comprises a core and a plurality of buildup layers. The core has an inner dielectric portion and the core outer conductive layer. The buildup layers are disposed over the core and have offset ablated regions reducing the thickness of the buildup layers in the ablated regions. Conductive material is plated on the buildup layers including within the ablated regions. The reduced thickness and increased plate area due to the ablated regions increases the capacitance between adjacent buildup layers. Processors and processing systems may take advantage of the increased capacitance in the package to draw more current and operate at higher data rates.

Abstract translation: 具有增加电容的封装包括芯和多个堆积层。 芯具有内绝缘部分和芯外导电层。 堆积层设置在芯上并且具有偏移的消融区域以减小烧蚀区域中积聚层的厚度。 导电材料镀在包括烧蚀区域内的积层上。 由于烧蚀区域减小的厚度和增加的板面积增加了相邻堆积层之间的电容。 处理器和处理系统可以利用增加的封装中的电容来绘制更多的电流并以更高的数据速率工作。