公开(公告)号：US20070263475A1

公开(公告)日：2007-11-15

申请号：US11383023

申请日：2006-05-12

Applicant: Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

Inventor： Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

IPC: G11C8/00

CPC classification number: G11C5/063 ,  G11C7/1048 ,  G11C7/1066

Abstract: A double-data-rate two synchronous dynamic random access (DDR2) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having a common output wherein a high-speed output path and a low-speed output path are coupled together by an output coupling and further coupled to the common output of the memory core.

Abstract translation: 双数据速率两同步动态随机存取（DDR2）存储器电路包括低速输入路径和通过输入耦合耦合到其上的高速输入路径并形成公共输入，公共输入耦合到存储器核心 存储器芯具有公共输出，其中高速输出路径和低速输出路径通过输出耦合耦合在一起并进一步耦合到存储器核心的公共输出端。

公开(公告)号：US20050285600A1

公开(公告)日：2005-12-29

申请号：US10879813

申请日：2004-06-29

Applicant: Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

Inventor： Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

IPC: G01R27/28 ,  G01R31/08 ,  G01R31/28

CPC classification number: G01R31/2853 ,  G01R27/28

Abstract: A method and apparatus are provided for implementing direct attenuation loss measurement in an electronic package. A sinusoidal voltage source signal of a selected frequency is coupled to an embedded transmission line test structure in the electronic package. Receive circuitry is coupled to the transmission line test structure for detecting amplitude of a received sinusoidal voltage source signal to identify attenuation loss through the transmission line test structure. An identified attenuation loss of the transmission line test structure is compared with a threshold value for verifying acceptable attenuation of the electronic package transmission line test structure.

Abstract translation: 提供一种用于在电子封装中实现直接衰减损耗测量的方法和装置。 所选频率的正弦电压源信号耦合到电子封装中的嵌入式传输线测试结构。 接收电路耦合到传输线测试结构，用于检测接收的正弦电压源信号的幅度，以通过传输线测试结构识别衰减损耗。 将传输线测试结构的确定的衰减损耗与用于验证电子封装传输线测试结构的可接受衰减的阈值进行比较。

公开(公告)号：US20050104602A1

公开(公告)日：2005-05-19

申请号：US10712742

申请日：2003-11-13

Applicant: Gerald Bartley ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

Inventor： Gerald Bartley ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

IPC: G01R27/04 ,  G01R27/28 ,  G01R31/02 ,  H04B3/46

CPC classification number: G01R27/04

Abstract: A method and apparatus are provided for implementing automated electronic package transmission line characteristic impedance verification. A sinusoidal voltage source is coupled to a transmission line test structure for generating a selected frequency. Impedance measuring circuitry is coupled to the transmission line test structure for measuring an input impedance with an open-circuit termination and a short-circuit termination. Characteristic impedance calculation circuitry is coupled to the impedance measuring circuitry receiving the input impedance measured values for the open-circuit termination and the short-circuit termination for calculating characteristic impedance. Logic circuitry is coupled to the characteristic impedance calculation circuitry for comparing the calculated characteristic impedance with threshold values for verifying acceptable electronic package transmission line characteristic impedance.

Abstract translation: 提供了一种用于实现自动化电子封装传输线特性阻抗验证的方法和装置。 正弦电压源耦合到用于产生选定频率的传输线测试结构。 阻抗测量电路耦合到传输线测试结构，用于测量具有开路端接和短路端接的输入阻抗。 特征阻抗计算电路耦合到阻抗测量电路，其接收用于开路端接的输入阻抗测量值和用于计算特性阻抗的短路端接。 逻辑电路耦合到特征阻抗计算电路，用于将计算的特性阻抗与用于验证可接受的电子封装传输线特性阻抗的阈值进行比较。

公开(公告)号：US20080031076A1

公开(公告)日：2008-02-07

申请号：US11872108

申请日：2007-10-15

Applicant: Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

Inventor： Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

IPC: G11C8/12

CPC classification number: G11C29/26 ,  G06F13/4243 ,  G11C5/04 ,  G11C8/12 ,  G11C29/32 ,  G11C2029/3202

Abstract: A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip. If not, the memory chip re-drives the address/command word on a first output. Write data is received as part of the address/command word or from a first data bus port. A bus clock is received and is used to receive and transmit information on the first input, the first output, the first data bus port and the second data bus port. The memory chip is incorporated into a design structure that is embodied in a computer readable medium used for designing, manufacturing, or testing the memory chip.

Abstract translation: 适用于存储芯片的菊花链的存储芯片。 存储器芯片在第一输入端接收地址/命令字，确定地址命令字是否被引导到存储器芯片; 如果是这样，则存储器芯片访问存储器芯片上的阵列。 如果不是，则存储器芯片在第一输出上重新驱动地址/命令字。 作为地址/命令字的一部分或从第一数据总线端口接收写入数据。 接收总线时钟并用于接收和发送关于第一输入，第一输出，第一数据总线端口和第二数据总线端口的信息。 存储器芯片被并入设计结构中，其体现在用于设计，制造或测试存储器芯片的计算机可读介质中。

公开(公告)号：US20070208463A1

公开(公告)日：2007-09-06

申请号：US11366881

申请日：2006-03-02

Applicant: Gerald Bartley ,  Moises Cases ,  Daniel de Araujo ,  Mark Maxson

Inventor： Gerald Bartley ,  Moises Cases ,  Daniel de Araujo ,  Mark Maxson

IPC: G05D11/00

CPC classification number: G06F1/26

Abstract: In an embodiment, a predicted voltage to supply to an electronic device is learned based on a dynamic voltage variation that occurs at the electronic device. The dynamic voltage variation occurs in response to the electronic device processing a functional event, and the predicted voltage is supplied to the electronic device in response to observing the functional event on a bus that is connected to the electronic device. In response to observing the dynamic voltage variation, the predicted voltage that is associated with the functional event is modified based on the dynamic voltage variation. Then, on the next occurrence of the functional event, the predicted voltage is supplied to the electronic device. In this way, voltage transients at the electronic device are controlled.

Abstract translation: 在一个实施例中，基于在电子设备处发生的动态电压变化来学习向电子设备提供的预测电压。 响应于电子设备处理功能事件而发生动态电压变化，并且响应于观察连接到电子设备的总线上的功能事件，将预测电压提供给电子设备。 响应观察动态电压变化，基于动态电压变化修改与功能事件相关联的预测电压。 然后，在下一次发生功能事件时，向电子设备提供预测电压。 以这种方式，控制电子设备处的电压瞬变。

公开(公告)号：US20070138653A1

公开(公告)日：2007-06-21

申请号：US11304138

申请日：2005-12-15

Applicant: Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

Inventor： Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

IPC: H01L23/48

CPC classification number: H01L23/50 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/10253 ,  H01L2924/13034 ,  H01L2924/1461 ,  H01L2924/15311 ,  H05K1/0219 ,  H05K1/0262 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/049 ,  H05K2201/10053 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A power control method and power control structures are provided for managing a plurality of voltage islands of a functional chip. The power control structure includes a supply control and partition chip positioned between a substrate carrier and a functional chip including a plurality of voltage islands. The supply control and partition chip includes a plurality of first electrical connections to the functional chip including the plurality of voltage islands. The supply control and partition chip includes a plurality of second electrical connections to the substrate carrier. Power applied to predefined ones of the first electrical connections to the functional chip are selectively switched on and off by the supply control and partition chip.

Abstract translation: 提供功率控制方法和功率控制结构，用于管理功能芯片的多个电压岛。 功率控制结构包括位于衬底载体和包括多个电压岛的功能芯片之间的供电控制和分隔芯片。 电源控制和分配芯片包括与包括多个电压岛的功能芯片的多个第一电连接。 供应控制和分隔芯片包括到基板载体的多个第二电连接。 施加到功能芯片的第一电连接中的预定义的电力的电力被供电控制和分配芯片选择性地接通和关断。

公开(公告)号：US20060190668A1

公开(公告)日：2006-08-24

申请号：US11064745

申请日：2005-02-24

Applicant: Giora Biran ,  Matthew Cushing ,  Robert Drehmel ,  Allen Gavin ,  Mark Kautzman ,  Jamie Kuesel ,  Ming-I Lin ,  David Luick ,  James Marcella ,  Mark Maxson ,  Eric Mejdrich ,  Adam Muff ,  Clarence Ogilvie ,  Charles Woodruff

Inventor： Giora Biran ,  Matthew Cushing ,  Robert Drehmel ,  Allen Gavin ,  Mark Kautzman ,  Jamie Kuesel ,  Ming-I Lin ,  David Luick ,  James Marcella ,  Mark Maxson ,  Eric Mejdrich ,  Adam Muff ,  Clarence Ogilvie ,  Charles Woodruff

IPC: G06F13/36

CPC classification number: G06F13/4059

Abstract: A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.

Abstract translation: 高速计算机处理器系统具有用于图形处理器的高速接口。 优选实施例将来自国际商业机器公司（IBM）的称为Giga-Processor Ultralite（GPUL）110的PowerPC微处理器与多芯片模块上的高速接口相结合。

公开(公告)号：US20050125752A1

公开(公告)日：2005-06-09

申请号：US10731064

申请日：2003-12-09

Applicant: Todd Cannon ,  William Csongradi ,  Roger Gravrok ,  Mark Maxson ,  David Pease ,  Ryan Schlichting ,  Patrick Sobotta

Inventor： Todd Cannon ,  William Csongradi ,  Roger Gravrok ,  Mark Maxson ,  David Pease ,  Ryan Schlichting ,  Patrick Sobotta

IPC: G06F17/50 ,  H05K1/02 ,  H05K3/00

CPC classification number: G06F17/5036 ,  H05K1/0231 ,  H05K3/0005

Abstract: A method, apparatus and computer program product are provided for implementing automated detection of excess aggressor shape capacitance coupling in printed circuit board layouts. A PCB design file containing an electronic representation of a printed circuit board design is received. A list of candidate shapes is identified. The candidate shapes are disposed on layers adjacent to aggressor planes. A capacitance coupling the candidate shapes to adjacent aggressor planes is calculated. A ratio of the calculated capacitance and a decoupling capacitance connecting the candidate shapes to a reference plane is determined. The PCB design file containing an electronic representation of a printed circuit board design includes shape data and text data that are extracted to produce a list of shapes' names, areas, locations and planes; and includes data defining thickness and relative permittivity of the dielectric layers used for calculating the effective capacitance is an inter-layer parallel-plate effective capacitance.

Abstract translation: 提供了一种方法，装置和计算机程序产品，用于实现印刷电路板布局中的多余侵略形状电容耦合的自动检测。 接收包含印刷电路板设计的电子表示的PCB设计文件。 识别候选形状的列表。 候选形状设置在与侵略者平面相邻的层上。 计算将候选形状耦合到相邻攻击者平面的电容。 确定所计算的电容和将候选形状连接到参考平面的去耦电容的比率。 包含印刷电路板设计的电子表示的PCB设计文件包括提取的形状数据和文本数据以产生形状名称，区域，位置和平面的列表; 并且包括用于计算有效电容的介电层的厚度和相对介电常数的数据是层间平行板有效电容。

公开(公告)号：US20060236277A1

公开(公告)日：2006-10-19

申请号：US11089472

申请日：2005-03-24

Applicant: Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

Inventor： Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

IPC: G06F17/50 ,  G06F9/45 ,  H03K17/693

CPC classification number: G06F17/5068 ,  G06F2217/78

Abstract: A method, apparatus and computer program product are provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package physical design data are identified. The identified instances of vertically coupled noise are quantified. Then the electronic package physical design data are modified to limit the vertically coupled noise.

Abstract translation: 提供了一种用于通过电子封装设计中的网格平面实现垂直耦合噪声控制的方法，装置和计算机程序产品。 接收电子封装物理设计数据。 识别电子封装物理设计数据中垂直耦合噪声的实例。 所确定的垂直耦合噪声的实例被量化。 然后修改电子封装物理设计数据，以限制垂直耦合噪声。

公开(公告)号：US20050264380A1

公开(公告)日：2005-12-01

申请号：US10857742

申请日：2004-05-28

Applicant: Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

Inventor： Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

IPC: H01P3/12 ,  H05K1/02 ,  H05K3/00

CPC classification number: H01P3/12 ,  H05K1/0237 ,  H05K1/0272 ,  H05K3/0061 ,  H05K2201/037

Abstract: A method and stiffener-embedded waveguide structure are provided for implementing enhanced data transfer for printed circuit board applications. At least one microwave channel is defined within a stiffener. The microwave channel provides a high frequency path for data transfers. Use of the waveguide channel in the stiffener for data transfers can replace or supplement otherwise required transmission paths in an associated printed circuit board.

Abstract translation: 提供了一种用于实现印刷电路板应用的增强型数据传输的方法和加强肋嵌入式波导结构。 在加强件内限定至少一个微波通道。 微波通道为数据传输提供了高频路径。 在加强件中用于数据传输的波导通道的使用可替代或补充相关印刷电路板中所需的传输路径。