Multiple rate architecture for wireline communication system
    1.
    发明申请
    Multiple rate architecture for wireline communication system 审中-公开
    用于有线通信系统的多速率架构

    公开(公告)号:US20080008255A1

    公开(公告)日:2008-01-10

    申请号:US11483963

    申请日:2006-07-10

    CPC classification number: H04L27/2626 H04L25/14 H04L27/2647

    Abstract: A discrete multitone (DMT) transceiver communicates with multiple channels generates and receives DMT symbols each having a duration of a timeslot. A transmitter portion of the transceiver includes a symbol processor which generates symbols for multiple channels sequentially, and stores the generated symbols in a buffer until they are transmitted. A receiver portion simultaneously receives symbols on multiple channels and stores the symbols in a buffer, from which the symbols on different channels are read and processed sequentially. To reduce the rate of communication on a given channel, the symbol processors may be idle in respect of some of the timeslots corresponding to that channel. The transceiver may alternatively be an OFDM transceiver.

    Abstract translation: 离散多音(DMT)收发器与多个通道通信产生和接收每个具有时隙持续时间的DMT码元。 收发器的发射机部分包括符号处理器,其顺序地产生多个信道的符号,并将生成的符号存储在缓冲器中直到它们被发送。 接收机部分同时在多个信道上接收符号并且将符号存储在缓冲器中,从该信号缓冲器中顺序地读取和处理不同信道上的符号。 为了降低给定信道上的通信速率,符号处理器可能对于与该信道相对应的某些时隙而言是空闲的。 收发器可以可选地是OFDM收发器。

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