High-voltage ESD protection device
    1.
    发明授权
    High-voltage ESD protection device 有权
    高压ESD保护装置

    公开(公告)号:US08803280B2

    公开(公告)日:2014-08-12

    申请号:US13276242

    申请日:2011-10-18

    Applicant: Qing Su

    Inventor: Qing Su

    CPC classification number: H01L27/0262 H01L29/735 H01L29/7436 H02H9/046

    Abstract: The present invention discloses a high-voltage ESD protection device including a silicon controlled rectifier and a first PNP transistor. The silicon controlled rectifier includes a high-voltage P-well and N-well; a first N+ and P+ diffusion region are formed in the high-voltage P-well; a second N+ and P+ diffusion region are formed in the high-voltage N-well. The first PNP transistor comprises an N-type buried layer; a low-voltage N-well formed in the N-type buried layer; and a base, emitter and collector formed in the low-voltage N-well. The base and emitter are shorted together; the collector is shorted to the second N+ diffusion region and the second P+ diffusion region; the first N+ diffusion region is shorted to the first P+ diffusion region to act as a ground terminal. The high-voltage ESD protection device can effectively adjust the ESD trigger voltage and improve the snapback sustaining voltage after the device is switched on.

    Abstract translation: 本发明公开了一种包括可控​​硅整流器和第一PNP晶体管的高压ESD保护器件。 可控硅整流器包括高压P阱和N阱; 在高电压P阱中形成第一N +和P +扩散区; 在高电压N阱中形成第二N +和P +扩散区。 第一PNP晶体管包括N型掩埋层; 在N型掩埋层中形成的低压N阱; 以及形成在低压N阱中的基极,发射极和集电极。 基极和发射极短接在一起; 集电极与第二N +扩散区和第二P +扩散区短路; 第一N +扩散区与第一P +扩散区短路,作为接地端。 高压ESD保护器件可以有效地调整ESD触发电压,并在器件接通后提高恢复保持电压。

    IBUPROFEN-BASED COMPOUND, PREPARATION METHOD, USE, AND FORMULATION OF THE SAME
    2.
    发明申请
    IBUPROFEN-BASED COMPOUND, PREPARATION METHOD, USE, AND FORMULATION OF THE SAME 审中-公开
    基于IBUPROFEN的化合物,其制备方法,使用和其制备

    公开(公告)号:US20140112978A1

    公开(公告)日:2014-04-24

    申请号:US14124390

    申请日:2012-05-23

    Abstract: Disclosed are compounds based on ibuprofen, their preparation methods, uses and pharmaceutical preparation. The compounds have structures shown as formula (1), wherein, m, n are integers and fulfill the requirements of 0≦n≦6, 0≦m≦6, respectively. The preparation methods for the compounds based on ibuprofen are as follows: contacting and reacting 2-(4-isobutyl-phenyl) propionic acid to have contact reaction with a solution of an organic acid ester in the presence of a catalyst under substitution reaction conditions The present compounds can be used to prepare nonsteroidal anti-inflammatory drugs. The preparation can be preparation of fat emulsion, liposome, and dried emulsion and so on.

    Abstract translation: 公开了基于布洛芬的化合物,其制备方法,用途和制药。 化合物具有式(1)所示的结构,其中m,n为整数,并分别满足0≦̸ n≦̸ 6,0< lE; m≦̸ 6的要求。 基于布洛芬的化合物的制备方法如下:在取代反应条件下,在催化剂存在下,使2-(4-异丁基 - 苯基)丙酸与有机酸酯的溶液接触反应。 本化合物可用于制备非甾体抗炎药物。 该制剂可制备脂肪乳剂,脂质体和干乳液等。

    METHOD FOR TRACE PHOSPHATE REMOVAL FROM WATER USING COMPOSITE RESIN
    3.
    发明申请
    METHOD FOR TRACE PHOSPHATE REMOVAL FROM WATER USING COMPOSITE RESIN 审中-公开
    使用复合树脂从水中去除磷酸盐的方法

    公开(公告)号:US20110155669A1

    公开(公告)日:2011-06-30

    申请号:US13061521

    申请日:2009-08-10

    CPC classification number: C02F1/288 C02F2101/105 C02F2303/16

    Abstract: The invention discloses a novel method for trace phosphate removal from water by using a composite resin. Firstly, adjusting the pH value of the raw water to 5.0˜9.0 and prefiltering the water, then leading the filtrate through an absorption tower packed with the composite resin, the trace phosphate in the water is therefore absorbed onto the composite resin; stopping the absorption run when it reaches the leakage point, using a binary NaOH-NaCl solution as the regenerant of the exhausted sorbent, followed by rinsing the composite resin-filled absorption tower with saturated carbon dioxide solution to regenerate the resin. In this invention, a composite resin with nanosized hydrated ferric oxide (HFO) or hydrous manganese dioxide (HMO) particles loaded on its surface is adopted as the absorbent for enhanced phosphate removal from water. A significant decrease of phosphate content in the effluent from this treatment system is found from 0.05-20 ppm to less than 20 ppb (calculated in P), despite of the coexisting competing anions as sulfate, chloride, and hydrocarbonate at much higher molar concentrations than phosphate. This invention is characteristic of large treatment capacity and efficient regeneration for repeated use of the absorbent.

    Abstract translation: 本发明公开了一种利用复合树脂从水中去除痕量磷酸的新方法。 首先,将原水的pH值调整至5.0〜9.0,并对水进行预过滤,然后使滤液通过填充复合树脂的吸收塔,水中的微量磷酸盐被吸收到复合树脂上; 使用二元NaOH-NaCl溶液作为排出的吸附剂的再生剂停止吸收运行,然后用饱和二氧化碳溶液冲洗复合树脂填充的吸收塔以再生树脂。 在本发明中,采用纳米级水合氧化铁(HFO)或含水二氧化锰(HMO)颗粒装载在其表面上的复合树脂作为增强磷酸盐从水中除去的吸收剂。 发现来自该处理系统的流出物中的磷酸盐含量显着降低,从0.05-20ppm至小于20ppb(以P计算),尽管以高于摩尔浓度的硫酸盐,氯化物和碳酸氢盐共存阴离子, 磷酸盐。 本发明的特征在于反复使用吸收剂的大的处理能力和有效的再生。

    FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC
    4.
    发明申请
    FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC 失效
    IC的平均关键区域的快速评估

    公开(公告)号:US20080148196A1

    公开(公告)日:2008-06-19

    申请号:US12032313

    申请日:2008-02-15

    CPC classification number: G06F17/5068

    Abstract: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

    Abstract translation: 用于近似布局或布局区域的平均临界区域的方法和装置,涉及在感兴趣的所有对象段上求和相应于依赖于对象的特定布局参数的关键区域贡献值,每个贡献值是代表性的 并且被定义为使得对于多个缺陷尺寸中的每个缺陷尺寸,并且对于特定缺陷类型,贡献值集合地计数由于感兴趣的对象片段而产生的所有关键区域一次。

    Fast evaluation of average critical area for IC layouts
    5.
    发明授权
    Fast evaluation of average critical area for IC layouts 有权
    快速评估IC布局的平均关键区域

    公开(公告)号:US07346865B2

    公开(公告)日:2008-03-18

    申请号:US10978946

    申请日:2004-11-01

    CPC classification number: G06F17/5068

    Abstract: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

    Abstract translation: 用于近似布局或布局区域的平均临界区域的方法和装置,涉及在感兴趣的所有对象段上求和相应于依赖于对象的特定布局参数的关键区域贡献值,每个贡献值是代表性的 并且被定义为使得对于多个缺陷尺寸中的每个缺陷尺寸,并且对于特定缺陷类型,贡献值集合地计数由于感兴趣的对象片段而产生的所有关键区域一次。

    DISKDRIVE BRACKET MOUNTING STRUCTURE
    6.
    发明申请
    DISKDRIVE BRACKET MOUNTING STRUCTURE 审中-公开
    DISKDRIVE支架安装结构

    公开(公告)号:US20070210224A1

    公开(公告)日:2007-09-13

    申请号:US11308163

    申请日:2006-03-09

    Applicant: Feng-Qing Su

    Inventor: Feng-Qing Su

    CPC classification number: G11B33/123

    Abstract: A diskdrive bracket mounting structure includes a bracket, a hexagonal copper column set at the bottom side of the bracket, a master cushion mounted in a mounting through hole of the bracket and sandwiched between the bracket and the hexagonal copper column, a supplementary cushion supported on the top side of the bracket around a part of the master cushion, and a P-head screw inserted through a through hole of the supplementary cushion and a through hole of the master cushion and threaded into a screw hole of the hexagonal copper column to affix the bracket to the hexagonal copper column, allowing the diskdrive bracket mounting structure to provide both the function of classis ground as well as the function of digital ground.

    Abstract translation: 磁盘驱动器支架安装结构包括支架,设置在支架底部的六边形铜柱,安装在支架的安装通孔中并夹在支架和六角铜柱之间的主垫,支撑在支架上的辅助垫 支架围绕主衬垫的一部分的顶侧,以及插入辅助衬垫的通孔的P头螺钉和主衬垫的通孔并拧入六边形铜柱的螺孔中以贴附 支架到六角铜柱,允许磁盘驱动器支架安装结构提供等级接地的功能以及数字地面的功能。

    Predicting IC manufacturing yield by considering both systematic and random intra-die process variations
    7.
    发明申请
    Predicting IC manufacturing yield by considering both systematic and random intra-die process variations 有权
    通过考虑系统和随机的模内工艺变化来预测IC制造产量

    公开(公告)号:US20070174797A1

    公开(公告)日:2007-07-26

    申请号:US11339184

    申请日:2006-01-24

    Abstract: One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.

    Abstract translation: 本发明的一个实施例提供了一种系统,其预测半导体晶片内的管芯的制造成品率。 在操作期间,系统首先接收模具的物理布局。 接下来,系统将模具分割成瓦片阵列。 然后,该系统计算质量指示值的系统变化,以基于模具的物理布局描述整个瓦片阵列上的过程参数。 接下来,系统将质量指示参数的随机变量应用于瓦片阵列中的每个瓦片。 最后,系统基于系统变化和随机变量得到了模具的制造成品率。

    Convolution computation for many-core processor architectures
    8.
    发明授权
    Convolution computation for many-core processor architectures 有权
    多核处理器架构的卷积计算

    公开(公告)号:US08458635B2

    公开(公告)日:2013-06-04

    申请号:US12631167

    申请日:2009-12-04

    CPC classification number: G06F17/5072 G06F17/50 G06F2217/68

    Abstract: A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of processor cores. A convolution operation of the kernel and the evaluation points in the sector is executed. The convolution operation includes iteratively loading parts of the basis data set, called a stride, into space available in shared memory given the size of the layout data specifying the sector. A plurality of threads is executed concurrently using the layout data for the sector and the currently loaded part of the basis data set. The iteration for the loading basis data set proceeds through the entire data set until the convolution operation is completed.

    Abstract translation: 内核在多核处理器系统中的布局的卷积包括识别包括多个评估点的布局的称为动态带的扇区。 指定布局扇区的布局数据被加载到由多个处理器核共享的共享存储器中。 执行内核和扇区中评估点的卷积运算。 卷积操作包括在给定指定扇区的布局数据的大小的情况下,将称为步幅的基础数据集的部分迭代地加载到共享存储器中可用的空间中。 使用用于扇区的布局数据和基础数据集的当前加载的部分来同时执行多个线程。 加载基础数据集的迭代通过整个数据集进行,直到卷积操作完成。

    Fast evaluation of average critical area for IC layouts
    9.
    发明授权
    Fast evaluation of average critical area for IC layouts 有权
    快速评估IC布局的平均关键区域

    公开(公告)号:US08205185B2

    公开(公告)日:2012-06-19

    申请号:US12542625

    申请日:2009-08-17

    CPC classification number: G06F17/5068

    Abstract: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

    Abstract translation: 用于近似布局或布局区域的平均临界区域的方法和装置,涉及在感兴趣的所有对象段上求和相应于依赖于对象的特定布局参数的关键区域贡献值,每个贡献值是代表性的 并且被定义为使得对于多个缺陷尺寸中的每个缺陷尺寸,并且对于特定缺陷类型,贡献值集合地计数由于感兴趣的对象片段而产生的所有关键区域一次。

    HIGH-VOLTAGE ESD PROTECTION DEVICE
    10.
    发明申请
    HIGH-VOLTAGE ESD PROTECTION DEVICE 有权
    高电压ESD保护器件

    公开(公告)号:US20120091503A1

    公开(公告)日:2012-04-19

    申请号:US13276242

    申请日:2011-10-18

    Applicant: Qing Su

    Inventor: Qing Su

    CPC classification number: H01L27/0262 H01L29/735 H01L29/7436 H02H9/046

    Abstract: The present invention discloses a high-voltage ESD protection device including a silicon controlled rectifier and a first PNP transistor. The silicon controlled rectifier includes a high-voltage P-well and N-well; a first N+ and P+ diffusion region are formed in the high-voltage P-well; a second N+ and P+ diffusion region are formed in the high-voltage N-well. The first PNP transistor comprises an N-type buried layer; a low-voltage N-well formed in the N-type buried layer; and a base, emitter and collector formed in the low-voltage N-well. The base and emitter are shorted together; the collector is shorted to the second N+ diffusion region and the second P+ diffusion region; the first N+ diffusion region is shorted to the first P+ diffusion region to act as a ground terminal. The high-voltage ESD protection device can effectively adjust the ESD trigger voltage and improve the snapback sustaining voltage after the device is switched on.

    Abstract translation: 本发明公开了一种包括可控​​硅整流器和第一PNP晶体管的高压ESD保护器件。 可控硅整流器包括高压P阱和N阱; 在高电压P阱中形成第一N +和P +扩散区; 在高电压N阱中形成第二N +和P +扩散区。 第一PNP晶体管包括N型掩埋层; 在N型掩埋层中形成的低压N阱; 以及形成在低压N阱中的基极,发射极和集电极。 基极和发射极短接在一起; 集电极与第二N +扩散区和第二P +扩散区短路; 第一N +扩散区与第一P +扩散区短路,作为接地端。 高压ESD保护器件可以有效地调整ESD触发电压,并在器件接通后提高恢复保持电压。

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