Abstract:
A tree stand includes a ladder portion having first and second rails, a tree-engaging member configured to engage a tree, and a mechanism being selectively variable in length operatively interconnecting the member and the first and second rails and controlling the distance between the member and the first and second rails. A platform is pivotably connected to the first and second rails.
Abstract:
A system may include a Graphics Processing Unit (GPU) and a Field Programmable Gate Array (FPGA). The system may further include a bus interface that is external to the FPGA, and that is configured to transfer data directly between the GPU and the FPGA without storing the data in a memory of a central processing unit (CPU) as an intermediary operation.
Abstract:
A tree stand includes a ladder portion having first and second rails, a tree-engaging member configured to engage a tree, and a mechanism being selectively variable in length operatively interconnecting the member and the first and second rails and controlling the distance between the member and the first and second rails. A platform is pivotably connected to the first and second rails.
Abstract:
A Random Access Memory (RAM) based Content Addressable Memory (CAM) architecture is disclosed. In an implementation, the CAM architecture includes a CAM data structure associated with a RAM to store one or more tags and associated data values. Each of the tags includes one or more bit fields which are utilized as an index for referencing a look-up table. One or more look-up tables may be realized for supporting memory operations facilitating efficient transfer modes available in the RAM.
Abstract:
A mobile server is wirelessly communicable with at least one remote input/output (I/O) device to form a wireless personal-area network (PAN). The mobile server has at least one application program interface (API) allowing an application of arbitrary implementation on the mobile server to recognize and control at least one service implemented by the remote I/O device.
Abstract:
Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.
Abstract:
Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.
Abstract:
A mobile server is wirelessly communicable with at least one remote input/output (I/O) device to form a wireless personal-area network (PAN). The mobile server has at least one application program interface (API) allowing an application of arbitrary implementation on the mobile server to recognize and control at least one service implemented by the remote I/O device.
Abstract:
A dataflow graph is split into sub-graphs referred to as configurations, each configuration comprising computational hardware containing elements that operate on operand sets. A configuration executes by consuming completed operand sets from a designated input tag space (e.g., in a content addressable memory) until the operand sets are exhausted. At that point, the configuration is replaced by another configuration. The execution of a configuration may be triggered by system events, including by the completion of one or more other configurations. Each configuration has a list of inputs on which it depends to form complete operand sets. As other configurations that provide an input complete, a dependency flag is set in each dependent configuration. As each flag is set, the complete set of flags is checked for that configuration; if all the input flags for any configuration are set, then that configuration is scheduled for execution.
Abstract:
A multi-tasking operating system and method updates PCI address values in an extension register to ensure that various threads utilize the correct values when accessing peripheral PCI devices. When application program threads require access to a PCI device, the operating system writes the high order bits of the PCI device address to two places: (1) the extension register of the PCI host bridge to allow immediate addressing of the PCI device, and (2) separate memory locations associated with the threads. When a context switch occurs from a first thread to a second thread, the operating system retrieves the stored value from the memory location associated with the second thread and writes the value to the extension register. In this manner, when the second thread requires access to its PCI device, the proper address value is already located in the extension register.