Tree stand and method of use thereof

    公开(公告)号:US11707059B2

    公开(公告)日:2023-07-25

    申请号:US16740457

    申请日:2020-01-12

    CPC classification number: A01M31/02

    Abstract: A tree stand includes a ladder portion having first and second rails, a tree-engaging member configured to engage a tree, and a mechanism being selectively variable in length operatively interconnecting the member and the first and second rails and controlling the distance between the member and the first and second rails. A platform is pivotably connected to the first and second rails.

    Direct communication between GPU and FPGA components
    2.
    发明授权
    Direct communication between GPU and FPGA components 有权
    GPU与FPGA组件之间的直接通信

    公开(公告)号:US09304730B2

    公开(公告)日:2016-04-05

    申请号:US13593129

    申请日:2012-08-23

    Abstract: A system may include a Graphics Processing Unit (GPU) and a Field Programmable Gate Array (FPGA). The system may further include a bus interface that is external to the FPGA, and that is configured to transfer data directly between the GPU and the FPGA without storing the data in a memory of a central processing unit (CPU) as an intermediary operation.

    Abstract translation: 系统可以包括图形处理单元(GPU)和现场可编程门阵列(FPGA)。 该系统还可以包括在FPGA外部的总线接口,并且被配置为直接在GPU和FPGA之间传送数据,而不将数据存储在中央处理单元(CPU)的存储器中作为中介操作。

    TREE STAND AND METHOD OF USE THEREOF
    3.
    发明申请

    公开(公告)号:US20200146278A1

    公开(公告)日:2020-05-14

    申请号:US16740457

    申请日:2020-01-12

    Abstract: A tree stand includes a ladder portion having first and second rails, a tree-engaging member configured to engage a tree, and a mechanism being selectively variable in length operatively interconnecting the member and the first and second rails and controlling the distance between the member and the first and second rails. A platform is pivotably connected to the first and second rails.

    Random Access Memory (RAM) Based Content Addressable Memory (CAM) Management
    4.
    发明申请
    Random Access Memory (RAM) Based Content Addressable Memory (CAM) Management 失效
    基于随机存取存储器(RAM)的内容可寻址存储器(CAM)管理

    公开(公告)号:US20070186036A1

    公开(公告)日:2007-08-09

    申请号:US11734168

    申请日:2007-04-11

    Applicant: Ray Bittner

    Inventor: Ray Bittner

    CPC classification number: G11C15/00

    Abstract: A Random Access Memory (RAM) based Content Addressable Memory (CAM) architecture is disclosed. In an implementation, the CAM architecture includes a CAM data structure associated with a RAM to store one or more tags and associated data values. Each of the tags includes one or more bit fields which are utilized as an index for referencing a look-up table. One or more look-up tables may be realized for supporting memory operations facilitating efficient transfer modes available in the RAM.

    Abstract translation: 公开了一种基于随机存取存储器(RAM)的内容可寻址存储器(CAM)架构。 在实现中,CAM架构包括与RAM相关联的CAM数据结构以存储一个或多个标签和相关联的数据值。 每个标签包括一个或多个比特字段,其被用作用于引用查找表的索引。 可以实现一个或多个查找表以支持促进RAM中可用的有效传输模式的存储器操作。

    Interfacing I/O Devices with a Mobile Server
    5.
    发明申请
    Interfacing I/O Devices with a Mobile Server 审中-公开
    将I / O设备与移动服务器连接

    公开(公告)号:US20070174515A1

    公开(公告)日:2007-07-26

    申请号:US11275490

    申请日:2006-01-09

    CPC classification number: H04M1/7253

    Abstract: A mobile server is wirelessly communicable with at least one remote input/output (I/O) device to form a wireless personal-area network (PAN). The mobile server has at least one application program interface (API) allowing an application of arbitrary implementation on the mobile server to recognize and control at least one service implemented by the remote I/O device.

    Abstract translation: 移动服务器与至少一个远程输入/输出(I / O)设备无线通信,以形成无线个人区域网络(PAN)。 移动服务器具有允许在移动服务器上应用任意实现的至少一个应用程序接口(API)来识别和控制由远程I / O设备实现的至少一个服务。

    Leveraging chip variability
    6.
    发明授权

    公开(公告)号:US08412882B2

    公开(公告)日:2013-04-02

    申请号:US12819100

    申请日:2010-06-18

    Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

    LEVERAGING CHIP VARIABILITY
    7.
    发明申请
    LEVERAGING CHIP VARIABILITY 有权
    杠杆切片变率

    公开(公告)号:US20110314210A1

    公开(公告)日:2011-12-22

    申请号:US12819100

    申请日:2010-06-18

    Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

    Abstract translation: 描述利用芯片的可变性的实施例。 芯片的不同区域在相同工作条件下的可靠性方面不同。 可以通过在芯片的不同区域上测量误差来捕获可变性。 可以改变影响或控制芯片上的错误可能性的物理因素。 例如,提供给芯片的电压可以设置在不同的水平。 在物理因素的每个级别,对芯片进行测试,以区域内的错误。 存储区域的误差统计的一些指示,然后用于调整芯片使用的功率,调整芯片的可靠性行为,以允许应用程序控制芯片的使用方式,以计算唯一识别芯片的签名, 等等

    Execution model for parallel computing
    9.
    发明申请
    Execution model for parallel computing 有权
    并行计算的执行模型

    公开(公告)号:US20060277391A1

    公开(公告)日:2006-12-07

    申请号:US11143307

    申请日:2005-06-01

    Applicant: Ray Bittner

    Inventor: Ray Bittner

    CPC classification number: G06F9/4494

    Abstract: A dataflow graph is split into sub-graphs referred to as configurations, each configuration comprising computational hardware containing elements that operate on operand sets. A configuration executes by consuming completed operand sets from a designated input tag space (e.g., in a content addressable memory) until the operand sets are exhausted. At that point, the configuration is replaced by another configuration. The execution of a configuration may be triggered by system events, including by the completion of one or more other configurations. Each configuration has a list of inputs on which it depends to form complete operand sets. As other configurations that provide an input complete, a dependency flag is set in each dependent configuration. As each flag is set, the complete set of flags is checked for that configuration; if all the input flags for any configuration are set, then that configuration is scheduled for execution.

    Abstract translation: 数据流图被分为称为配置的子图,每个配置包括包含操作数集合的元素的计算硬件。 通过从指定的输入标签空间(例如,在内容可寻址存储器)中消耗完成的操作数集,直到操作数集合被耗尽来执行配置。 在这一点上,配置被另一个配置所取代。 配置的执行可以由系统事件触发,包括完成一个或多个其他配置。 每个配置都有一个输入列表,它依赖于其形成完整的操作数集。 作为提供输入完成的其他配置,在每个相关配置中设置依赖标志。 当每个标志被设置时,对该配置检查完整的标志集合; 如果任何配置的所有输入标志都被设置,那么该配置被安排执行。

    Dynamic address windowing on a PCI bus
    10.
    发明申请
    Dynamic address windowing on a PCI bus 有权
    PCI总线上的动态地址窗口

    公开(公告)号:US20050165976A1

    公开(公告)日:2005-07-28

    申请号:US11082334

    申请日:2005-03-17

    CPC classification number: G06F13/4027

    Abstract: A multi-tasking operating system and method updates PCI address values in an extension register to ensure that various threads utilize the correct values when accessing peripheral PCI devices. When application program threads require access to a PCI device, the operating system writes the high order bits of the PCI device address to two places: (1) the extension register of the PCI host bridge to allow immediate addressing of the PCI device, and (2) separate memory locations associated with the threads. When a context switch occurs from a first thread to a second thread, the operating system retrieves the stored value from the memory location associated with the second thread and writes the value to the extension register. In this manner, when the second thread requires access to its PCI device, the proper address value is already located in the extension register.

    Abstract translation: 多任务操作系统和方法更新扩展寄存器中的PCI地址值,以确保各种线程在访问外围PCI设备时使用正确的值。 当应用程序线程需要访问PCI设备时,操作系统将PCI设备地址的高位位写入两个位置:(1)PCI主桥的扩展寄存器,以允许PCI设备的即时寻址,以及( 2)与线程相关联的单独内存位置。 当从第一个线程发生到第二个线程的上下文切换时,操作系统从与第二个线程相关联的存储器位置检索存储的值,并将该值写入扩展寄存器。 以这种方式,当第二线程需要访问其PCI设备时,适当的地址值已经位于扩展寄存器中。

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