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公开(公告)号：US09910822B2
公开(公告)日：2018-03-06
申请号：US14762040
申请日：2014-01-21
Applicant: Commissariat a l'energie atomique et aux energies alternatives , STmicroelectronics (Canada), Inc.
Inventor： Romain Lemaire , Fabien Clermidy , Michel Langevin , Charles Pilkington
IPC: H04L12/933 , H04L12/24 , H04L12/801 , H04L12/911 , G06F15/78
CPC classification number: G06F15/7825 , H04L41/0816 , H04L47/39 , H04L47/828 , H04L49/109
Abstract: A network interface for a first network on chip resource capable of interfacing a data processing unit in the first resource with the network, the network interface including an output communication controller including a mechanism detecting an indicator marking an end of communication between the first resource and at least one second resource with which a communication link is set up, and a mechanism outputting a signal indicating closure of the link to be sent to the second resource, after detection of an end of communication indicator.
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2.发明授权Interference cancellation and improved signal-to-noise ratio circuits, systems, and methods 有权干扰消除和改进的信噪比电路，系统和方法公开(公告)号：US09450624B2
公开(公告)日：2016-09-20
申请号：US14578119
申请日：2014-12-19
Applicant: STMICROELECTRONICS (CANADA), INC.
Inventor： Jose Augusto Lima , Antonio Mascioli
IPC: H04B1/10 , H04L25/03 , H04L27/233
CPC classification number: H04B1/10 , H04L25/0328 , H04L27/233
Abstract: Interference cancellation for wideband and narrowband communications systems is provided without apriori knowledge of statistical information about an interfering signal. In one embodiment a demodulator circuit can operate in an environment where a “no lock” situation would normally occur to remove the interference and acquire signals in low signal-to-noise ratio conditions and high signal-to-interference ration conditions. In other embodiments, performance is improved by introducing statistics of the interfering signal, and these statistics regarding the communications channel and interference properties (i.e., characteristics of the interfering signal) can be adaptive or “learned” in other embodiments.
Abstract translation: 提供宽带和窄带通信系统的干扰消除，而无需关于干扰信号的统计信息的知识。 在一个实施例中，解调器电路可以在通常发生“无锁定”情况的环境中操作，以消除干扰并获取低信噪比条件和高信噪比条件下的信号。 在其他实施例中，通过引入干扰信号的统计来提高性能，并且关于通信信道和干扰特性（即干扰信号的特性）的这些统计信息在其他实施例中可以是自适应的或“学习的”。
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公开(公告)号：US20140077845A1
公开(公告)日：2014-03-20
申请号：US14078190
申请日：2013-11-12
Applicant: STMicroelectronics (Canada) Inc.
Inventor： Anton Pelteshki , Hock Khor
IPC: H03K3/01
CPC classification number: H03K3/01 , H03F3/45179 , H03F3/45183 , H03F2203/45394 , H03F2203/45712 , H04L25/0266 , H04L25/0276 , H04L25/0282
Abstract: A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.
Abstract translation: 驱动器电路包括差分输入，差分输出，偏置节点，具有耦合到负输出节点的第一节点的第一T形线圈和耦合到电源电压源的第二节点，第二T形线圈具有 耦合到正输出节点的第一节点和耦合到电源电压源的第二节点，具有耦合在第一T形线圈的中心抽头和第一中间节点之间的电流通路的第一晶体管，具有电流 耦合在第二T形线圈的中心抽头和第二中间节点之间的路径，具有耦合在第一中间节点和地之间的电流路径的第三晶体管，以及连接在第二中间节点和地之间的电流路径的第四晶体管 。
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公开(公告)号：US09405511B2
公开(公告)日：2016-08-02
申请号：US14524774
申请日：2014-10-27
Inventor： John Hogeboom , Hock Khor , Matteo Alessio Traldi , Anton Pelteshki
CPC classification number: G06F7/724 , G06F5/16 , H03H17/06 , H04L25/0272 , H04L25/0288
Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.
Abstract translation: FIR发送架构使用多个驱动器分区，以允许具有不同延迟的信号被驱动器自身求和到输出信号中。 该架构包括第一多路复用器，多个延迟单元，多个符号块，开关块，第二多路复用器和多个驱动器。
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Patent Agency Ranking
5.发明申请INTERFERENCE CANCELLATION AND IMPROVED SIGNAL-TO-NOISE RATIO CIRCUITS, SYSTEMS, AND METHODS 审中-公开干扰消除和改进的信号噪声比率电路，系统和方法公开(公告)号：US20150180520A1
公开(公告)日：2015-06-25
申请号：US14578119
申请日：2014-12-19
Applicant: STMICROELECTRONICS (CANADA), INC.
Inventor： Jose Augusto Lima , Antonio Mascioli
IPC: H04B1/10
CPC classification number: H04B1/10 , H04L25/0328 , H04L27/233
Abstract: Interference cancellation for wideband and narrowband communications systems is provided without apriori knowledge of statistical information about an interfering signal. In one embodiment a demodulator circuit can operate in an environment where a “no lock” situation would normally occur to remove the interference and acquire signals in low signal-to-noise ratio conditions and high signal-to-interference ration conditions. In other embodiments, performance is improved by introducing statistics of the interfering signal, and these statistics regarding the communications channel and interference properties (i.e., characteristics of the interfering signal) can be adaptive or “learned” in other embodiments.
Abstract translation: 提供宽带和窄带通信系统的干扰消除，而无需关于干扰信号的统计信息的知识。 在一个实施例中，解调器电路可以在通常发生“无锁定”情况的环境中操作，以消除干扰并获取低信噪比条件和高信噪比条件下的信号。 在其他实施例中，通过引入干扰信号的统计来提高性能，并且关于通信信道和干扰特性（即干扰信号的特性）的这些统计信息在其它实施例中可以是自适应的或“学习的”。
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公开(公告)号：US20150136760A1
公开(公告)日：2015-05-21
申请号：US14538940
申请日：2014-11-12
Applicant: STMICROELECTRONICS (CANADA), INC. , STMICROELECTRONICS LTDA
Inventor： Jose Augusto LIMA , AMERICO PAULICCHI FILHO
CPC classification number: H05B6/686 , H05B6/668 , H05B6/705 , Y02B40/143 , Y02B40/146
Abstract: A microwave oven may include a housing defining an oven cavity therein configured to receive material to be heated, and a plurality of solid state microwave generating cells carried by the housing. At least one feedback circuit may be carried by the housing and configured to detect EM radiation within the oven cavity not absorbed by the material to be heated. A processor may be carried by the housing and coupled to the plurality of microwave beamforming cells and to the at least one feedback circuit. The processor may be configured to receive feedback from the at least one feedback circuit based upon the EM radiation not absorbed by the material to be heated, and control phase shifters of the beamforming cells to change the patterns of EM energy transmitted by antennas of the beamforming cells based upon the feedback received from the at least one feedback circuit.
Abstract translation: 微波炉可以包括限定其中构造成接收待加热材料的炉腔的壳体和由壳体承载的多个固态微波发生单元。 至少一个反馈电路可以由壳体承载并且被配置为检测未被待加热材料吸收的炉腔内的EM辐射。 处理器可以由外壳承载并耦合到多个微波波束形成单元和至少一个反馈电路。 处理器可以被配置为基于未被待加热材料吸收的EM辐射从所述至少一个反馈电路接收反馈，以及控制波束形成单元的移相器以改变由波束形成的天线发射的EM能量的模式 基于从所述至少一个反馈电路接收到的反馈。
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公开(公告)号：US08866514B2
公开(公告)日：2014-10-21
申请号：US14078190
申请日：2013-11-12
Applicant: STMicroelectronics (Canada) Inc.
Inventor： Anton Pelteshki , Hock Khor
CPC classification number: H03K3/01 , H03F3/45179 , H03F3/45183 , H03F2203/45394 , H03F2203/45712 , H04L25/0266 , H04L25/0276 , H04L25/0282
Abstract: A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.
Abstract translation: 驱动器电路包括差分输入，差分输出，偏置节点，具有耦合到负输出节点的第一节点的第一T形线圈和耦合到电源电压源的第二节点，第二T形线圈具有 耦合到正输出节点的第一节点和耦合到电源电压源的第二节点，具有耦合在第一T形线圈的中心抽头和第一中间节点之间的电流通路的第一晶体管，具有电流 耦合在第二T形线圈的中心抽头和第二中间节点之间的路径，具有耦合在第一中间节点和地之间的电流路径的第三晶体管，以及连接在第二中间节点和地之间的电流路径的第四晶体管 。
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8.发明申请NETWORK INTERFACE FOR A SoC COMPRISING AN IMPROVED COMMUNICATION CONTROLLER 有权用于包含改进的通信控制器的SoC的网络接口公开(公告)号：US20150319106A1
公开(公告)日：2015-11-05
申请号：US14762040
申请日：2014-01-21
Applicant: COMMISSARIAT Á L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES , STMICROELECTRONICS (CANADA), INC.
Inventor： Romain LEMAIRE , Fabien CLERMIDY , Michel LANGEVIN , Charles PILKINGTON
IPC: H04L12/933 , H04L12/911 , H04L12/24 , H04L12/801
CPC classification number: G06F15/7825 , H04L41/0816 , H04L47/39 , H04L47/828 , H04L49/109
Abstract: A network interface for a first network on chip resource capable of interfacing a data processing unit in the first resource with the network, the network interface including an output communication controller including a mechanism detecting an indicator marking an end of communication between the first resource and at least one second resource with which a communication link is set up, and a mechanism outputting a signal indicating closure of the link to be sent to the second resource, after detection of an end of communication indicator.
Abstract translation: 一种用于能够将第一资源中的数据处理单元与网络接口的第一片上资源的网络接口，所述网络接口包括输出通信控制器，所述输出通信控制器包括检测标识所述第一资源和所述第一资源之间的通信结束的指示符的机构 在检测到通信指示符的结束之后，建立通信链路的至少一个第二资源以及输出指示要发送到第二资源的链路的关闭的信号的机制。
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公开(公告)号：US20150074160A1
公开(公告)日：2015-03-12
申请号：US14524774
申请日：2014-10-27
Inventor： JOHN HOGEBOOM , HOCK KHOR , MATTEO ALESSIO TRALDI , ANTON PELTESHKI
CPC classification number: G06F7/724 , G06F5/16 , H03H17/06 , H04L25/0272 , H04L25/0288
Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.
Abstract translation: FIR发送架构使用多个驱动器分区，以允许具有不同延迟的信号被驱动器自身求和到输出信号中。 该架构包括第一多路复用器，多个延迟单元，多个符号块，开关块，第二多路复用器和多个驱动器。
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